( DAC 03 Item 16 ) ----------------------------------------------- [ 01/20/04 ]
Subject: Fishtail Focus
THE BETTER MOUSETRAP: What if, while linting, instead of just reporting the
timing errors you find to the engineer, you automatically generated all
the constraints needed for Design Compiler to synthesize your design? Of
course you'd need to somehow find all your timing exceptions and false paths
or your DC run could take days. This is what Fishtail Focus does. It's
basically Atrenta Spyglass taken to the next level. For frontend designers,
I cite Fishtail as one of the Best of DAC'03 Tools To Check Out.
I got a call from Fishtail and they told me that they automatically find
out the timing exceptions in the design by analyzing the RTL itself. My
antenna went up immediately. At first I was perplexed as how they can
do it, so I visited them at DAC.
Apparently, this company was started by ex-Synopsys guys and they
specialize in analyzing the control logic part of the design in order to
identify the false and multicycle paths for each different modes of the
design.
In our designs this is one of the areas where we spent a long time
finding out whether the path which is failing timing is real or not.
Most of the time if the path fails, it takes time to analyze it and then
report it to the guy who's doing timing analysis. This leads to many
iterations.
I think that the Fishtail guys have found a niche but significant market.
Not only this tool can be used to find the timing exceptions, but if used
during synthesis can improve the QoR of design. We are in the process of
evaluating this tool and awaiting results.
One other thing to note is that these guys also provide assertions for
each timing exception they find. These assertions can be incorporated in
the RTL. By using Verplex's Blacktie, the timing exceptions can be
validated, thus closing the loop.
- Himanshu Bhatnagar of Conexant Systems
We saw a demo of Focus from FishTail at DAC.
Strengths:
a) Focus generates golden timing constraints in SDC format (including
false paths & multicycle paths) from RTL and the clock spec. If we
understood what they said correctly, the false path info is based on
logically non-sensitizable paths. Also the multicycle path info
from Focus includes the number of cycles. This, by itself, is very
useful. (Especially, if you are a support engineer in an ASIC
company and you just receive the design data from your customer and
do not know much about the design with respect to timing. So, if
you receive RTL, this tool gives a lot of insight into the design
you are assigned to work on.)
b) When we use these constraints, we get shorter TAT and smaller area
in synthesis. DC works on proper, non-overconstrained constraints
and avoid unnecessary optimization. Focus seems to have a potential
to streamline the RTL hand-off flow, when a clear timing spec is
handed over to the downstream synthesis phase. It also optimizes
the synthesis optimization work.
c) Works OK for a large design. 10 minutes for 2M gates.
d) Overall, I recognize that Atrenta Spyglass and other RTL tools do
not provide what Focus has to offer. Unique and new.
Weaknesses:
a) Only Verilog (RTL and behavioral?) is supported. VHDL and gate
level execution are NOT supported (at least at DAC2003). Again, if
you are an ASIC support engineer, you often receive gate level
netlists. Without this gate level restriction, Focus would give you
a lot of useful information in timing for the design you have to
work on, even if it is a gate level netlist.
b) It seems that not all false and multi-cycle paths are reported by
the tool. A false path reported to be a false path by Focus is
guaranteed to be a false path, but not all those path are flagged
by the tool. Same thing for the multi-cycle paths. And the company
gave a 90% or so coverage number, claiming that the coverage
depends on the design.
c) Focus, as we heard, does not work for datapath elements such as
adders and multipliers. These blocks are seen as blackboxes.
I would like to hear about Focus from other people who evaluated or
used it.
- Toshiaki Tanaka of Kawasaki Microelectronics
I don't consider Fishtail a linting tool; thus, I wouldn't know how to
compare it to Atrenta SpyGlass or TransEDA. It is a tool which
generates timing exceptions (false and multicycle paths) by analyzing
the RTL and clock specification. It may have some linting capability,
but I really see it as a breakthrough methodology for automatically
generating timing exceptions. We are still working on supporting these
new exceptions in our flow; but once the pipecleaning is complete,
this product has real potential to improve QOR and also prevent falsely
reported timing violations from impacting schedule.
- Roger Carpenter of Broadcom
I evaluated Fishtail during Q3'03 using a core of size 70k and an
ASIC of size 400k gate count. The primary metrics I used to
evaluate the tool were - comprehensive exception generation, rate
of exception honoring by synthesis tool and the impact on QOR due
to Focus-generated exceptions.
In the beginning stages of the eval, Focus did not generate exceptions
for about 40% of the endpoints and Design Compiler didn't accept over
80% of the Fishtail generated exceptions.
Toward the end of the eval, the tool improvements resulted in successful
exception generation on 100% endpoints and DC honored over 99% of the
Focus-generated exceptions.
On the QoR front, marginal improvement of 3.7% in critical path
timing was seen during logic synthesis at the expense of about 2% in
increased area. (The exceptions were not carried forward to physical
design for a true QoR impact measurement due to some resource
constraints on our end.)
Other areas of improvement as a result of this eval worth mentioning
is in the selection of optimal default values on tool constraints thus
eliminating the need for related iterations for optimal analysis and
generation of constraints in ETA format.
- Chandra Moturu of Hewlett-Packard
FishTail technology is rather unique. It explores RTL and identifies
false paths which tend to consume a lot of designer time when trying
to close timing on a critical block to verify if failing paths are
false or not. If the tool works, it will help to accelerate synthesis
effort to close timing on critical blocks.
Another potential side benefit of this technology is to minimize area
by identifying all false paths and making sure the synthesis engine
does not sacrifice area and CPU time to close timing on those false
paths.
Again, we have neither used the tool nor evaluated Fishtail. This is
just a first impression we got from seeing the demo.
- Karim Arabi of PMC-Sierra
I have used Focus, Spyglass and Nova. Out of these three, I have used
Spyglass and Nova for linting purposes and to help maintain a consistent
RTL style.
The key strength of Focus is its ability to read in the RTL of a design
and detect multicycle and false paths in the design. The good news here
is that the tool can do this with minimal constraints and setup.
Obviously, the better the setup, the better the results, but extensive
setup of the design environment (especially for a beginner) is not
necessary.
Our internal DSP design has a pipeline with many modes and results in
several hundred multi-cycle and false paths. I have been using Focus as a
tool to discover these timing exceptions automatically.
I haven't used any other tool for this purpose nor do I know of any other
tool out there that does this.
I started working with Fishtail because every change in our DSP
architecture cost me several months in timing closure. Specifically with
identifying timing exceptions in the design. I started evaluating Focus
in an effort to speed up this phase of the design.
At this point we are confident that the timing exceptions generated by
Focus are real. When in doubt we have been able to verify the paths by
using the sensitizing conditions that are automatically provided. The
next time we touch the DSP architecture I plan to use Focus. I estimate
it'll reduce months in the schedule for timing exceptions to no probably
more than 2 weeks.
The only downside I've seen with Fishtail is that the output of Focus,
when run on the entire design was very large in our case -- running into
several hundred false paths. (OK, so timing exceptions of this size would
crash any timing tool out there!) So we run Focus interactively - Run
Primetime - take the violating endpoint - run Focus - correlate with
results for false and multicycle exceptions - back to Run PrimeTime.
Fishtail has been working with us and using our input on improvements.
At this point we're happy with the tool. Anything to make the tool give
us only the exceptions that violate timing would probably be the missing
piece (if there is one.)
- Sameer Rao of Conexant Systems
We are in the early stages of evaluating Fishtail's Focus.
Focus is used to automatically generate timing constraints (false paths,
multicycle paths). To my knowledge, Focus is the only tool in the
marketplace that can do this.
We have setup Focus and used it to generate timing constraints. We
have not yet validated the accuracy/completeness of the constraints.
As the constraints are what the tool is all about, I am unable to
provide you a meaningful opinion on how good the tools results are.
I can tell you that Focus is fairly easy to setup and use. As can be
expected, the tool does have really long run times.
- Karthik Rajan of Microchip Technology, Inc.
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