( DAC 03 Item 14 ) ----------------------------------------------- [ 01/20/04 ]
Subject: Verisity SureCov, TransEDA, VeriEZ, Synopsys Leda & CoverMeter
THE NETSCAPE PROBLEM: Since Cadence, Synopsys, and ModelTech are going nuts
adding-anything-they-can-to-make-a-sale, these free built-in linters and
code coverage tools have been slowing killing off the small linter start-ups.
It's really hard to sell against free; hence these start-ups losing interest
in working any more in the linter / code coverage niche.
We are using SureCov and are quite happy with it except for the Verilog
2001 support. The number of Verilog 2001 features covered in the current
version is still rather poor and improvment in that field is very slow
coming. Verisity doesn't seem to be very interested in that tool
anymore.
Their business is focussed on Specman and that's it. Same for their
linter, Surelint, which is not upgraded anymore and therefore will never
support Verilog 2001.
We are thinking about moving to HDLScore (Summit code coverage tool
which has been bought by Cadence and now part of NC-Sim). It is not as
easy to use it as SureCov and not integrated at all within NC-Sim at
the moment but should fully support Verilog 2001 in the LDC5.1.
- Laurent Claudel
I have used Verisity's SureCov, and TransEDA. SureCov is a better tool
with more intuitive interfaces etc... Unfortunately, SureCov doesn't
support VHDL which I'm currently working with so I'm stuck w/ TransEDA.
- Mike Nelson of Alcatel
SureCov is being used in my company but I have not touched it myself.
Heard some good stuff about it. Our EDA guys did some comparisons and
thought Cadence HDLScore was better as it could handle VHDL and Verilog.
They liked both of them over the old Cadence NC-COV. Right now, we are
moving to the Synopsys VCS code coverage tool and a person in my group
likes it. Right now he does not have a choice of tools, so you do end up
liking it. :-)
- [ An Anon Engineer ]
We focused more on the SureCov results towards the end of verification
to confirm high block and toggle coverage. We did not strive for
exhaustive arc coverage. Less than 100% block and toggle coverage
usually resulted in another test case.
We haven't compared SureCov against other code coverage tools.
- Tom Hergenrother of Calix
We use Nova from Synopsys/Avanti. We find it fast, useful and
expandable. We write many of the lint rules ourselves. Some bugs exist.
We get fair support from Synopsys, even though they are pushing Leda. We
tested Leda and found it bad -- slow, not user friendly and full of bugs.
SureCov -- we use it extensively and find it very good except for one
major drawback/bug -- it reports glitches, including zero-delay glitches
but not only, at covered line. This is a bug since if a value on a
signal was not sampled in an FF, then this value was not really covered.
Talking to Verisity did not help as they see this as low priority and do
not realize this is a severe bug. SureCov reports way too high coverage
than reality. We're now considering moving to HDLscore, now part of
Cadence Incisive.
- [ An Anon Engineer ]
TransEDA's coverage tool, VNCover, is pretty comprehensive, although
since I almost always run EDA tools from scripts, the flashy GUI is kind
of wasted on me. One thing I have found it doesn't cope with (currently,
at any rate) is when I've used VHDL 'if-generate' statements to exclude
blocks of code from elaboration depending on the value of a generic
parameter. In this case the excluded code (with zero coverage)
contributes to the final coverage figures, even though it's not
elaborated and therefore isn't part of the simulated design.
- [ An Anon Engineer ]
Linters & Code Coverage
Atrenta emphasizes that their tool is definitely not a linter, although
it sure sounds a lot like one. Actually it synthesizes to generic gates
and has some fancy stuff under that hood so it can do things a regular
linter cannot, and costs more as a result; hence their concern over
being lumped in that category. New for this year is a low power policy
checker. They can also check for proper synchronization across clock
domains (using any of 9 standard synchronization techniques). It also
checks for level shifters between voltage domains. They say a 1 M gate
design takes about an hour.
Synopsys sells the linter from the French company Leda that they
acquired. In the last year they've worked to better organize rules.
When a linter claims 2 thousand rules, it's likely that it's really
200 rules each in ten different categories. Cross-correlating them
makes the users job of establishing baseline rules much easier.
VeriEZ sells a linter for openVera, which I believe is the only one on
the market.
TransEDA sells a code coverage tool that in my experience is extremely
easy to learn. This year they've deglitched waveforms for simulation
artifacts to prevent false coverage metrics. They also have now added
Sugar/PSL property coverage, which are shown in the same GUI as code
coverage. The properties are extracted from VCD. You need to simulate
only once and then you can then change your properties and re-extract
coverage from the VCD. They plan to add coverage metrics for partial
coverage of properties.
Summit sells another code coverage tool that is also very capable.
Cadence is now including this tool for free in their Incisive simulator
offering.
Synopsys sells CoverMeter, a code coverage tool which is now included
for free with VCS.
Lots of new freebies from simulator vendors, particularly Cadence's
Incisive upgrade to NC-Sim. I don't know if this stuff is any good,
but you get a ton of extras for very little money. If you are
selling just a plain vanilla simulator you may have problems, and
people selling code coverage, linting, etc. could get hurt.
- John Weiland of Intrinsix
Verisity SureCov is a good code coverage tool but it's hard to justify
buying one when there one free with most simulators.
- Kevin Jones of Rambus
Linters and code coverage tools make designers feel good even if they are
not the solution. These will stay until we define design certification
approaches.
- Ahmed Jerraya
We just turned on the code coverage that comes bundled with Cadence's
NC-Verilog. It doesn't do stuff like expression coverage, but it gives
us a rough idea of what we are checking. There are some opinions around
here about how coverage not being a very good quality metric. Haven't
looked at other tools.
- Tomoo Taguchi of Hewlett Packard
With the latest version of Cadence NC-Sim (and probably Synopsys VCS,
although I haven't checked), you essentially get code-coverage for free.
It would probably make sense to use the built-in version as it *should*
run much faster.
- [ An Anon Engineer ]
3rd party code coverage tools are too expensive for what they offer.
ModelSim code coverage works great. Easy to setup. Easy to view
results. It's free. ModelSim performance analyzer rocks, too.
- Kevin Hubbard of Siemens
It is tough to justify buying a line coverage tool when both VCS and
NC-Verilog are shipping with one built in.
- [ An Anon Engineer ]
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