( DAC 03 Item 13 ) ----------------------------------------------- [ 01/20/04 ]
Subject: Avery, Innologic, Averant, Safelogic, Synapticad, Obsidian, Jeda
YET MORE ASSERTION TOOLS: Like the flu in a daycare center, assertion based
functional verification tools are everywhere! The funny thing is that you'd
think there'd have been some sort of Darwinian survial-of-the-fittest die
off here, but it has yet to happen. Safelogic is the new company to join
this overcrowded field this year.
Safelogic also looked interesting. I think their product is pretty
immature and it only supports VHDL but they are on to something with
their PSL formal property checker. Add support for arbitrary start
states in the analysis and it is beginning to be interesting.
- Anders Nordstrom of Elliptic Semiconductor
Avery Design sells TestWizard, which provides transaction based
verification using assertions, constrained random vector generation
and functional coverage (sounds familiar). Their difference is that
they provide extensions to Verilog or VHDL, so that the user doesn't
need to learn a separate Hardware Verification Language. They just
announced a tool called Insight, which takes up when TestWizard runs
out of steam. The input is assertions coverage data from TestWizard
and the output is a testbench that exercises assertion that were missed
by the existing tests; it generates tests to cover assertions. It
combines logic and symbolic simulation with a SAT solver (no, I'm not
exactly sure what that means, either). They are looking for beta
customers now and believe the tool will not be particularly easy
to learn.
Safelogic sells two assertion based tools. The first plugs into Modelsim
to allow PSL/Sugar assertions with property coverage and constrained
random vectors. They do not currently support NC-Sim or VCS. The second
tool is a formal property checker that can go a couple of hundred cycles
deep. They say their combination of simulation and static checking gives
them an edge, and their tools are very easy to use.
Averant sells a static verification tool called Solidify, and has added
new automatic checks that are about the same as Magellan (and other
people) - X assignments, floating busses, tri-state contention, register
toggle, dead code, deadlock, clock domain issues, out-of-range index,
etc. They maintain their language (HPL) is superior to PSL/Sugar but
they now support OVL. For assertions that can't be proved or disproved
the tool outputs Verilog monitors (OVA) or e language assertions. They
do full clock inferencing for easier setup and for initialization you
need only initialize the top level and they infer the initialization
sequence for the sub-blocks.
Innologic's marketing for their symbolic simulation has changed a lot.
I am reminded of model checkers. When model checkers first came into
use, they required one to master an obscure language and use one's
imagination about how one could apply this technology. The tools had a
dedicated following of true believers but never caught on with the
masses. Then maybe two years ago several vendors came out with simple,
GUI driven systems that allowed maybe the ten most common uses for model
checking, without any programmability. Recently some tools have come out
that have the common uses built in but allow one to program custom uses.
Innologic seems to be following this path. Two years ago they had a
general purpose tool that was nearly impossible to explain in a one hour
demo (I had several intelligent friends who went through the demo and
did the smile-and-nod thing throughout). They now sell the tools as an
answer for full custom verification and de-emphasize the details of the
technology, which most people won't understand and probably don't need to
understand. They say they can compare behavioral (non-synthesizable)
descriptions to SPICE netlists -- not a common capability. If there is
a problem, they output an example that demonstrates the problem. Their
hierarchical compression allows them to do huge designs if the designs
are repetitive (like a memory). Their largest design to date is 1.7
billion transistors. Some power users still use the basic symbolic
simulation engine directly. Some FPGA users use it for fast transistor
level simulation.
TransEDA sells a code coverage tool that in my experience is extremely
easy to learn. This year they've deglitched waveforms for simulation
artifacts to prevent false coverage metrics. They also have now added
Sugar/PSL property coverage, which are shown in the same GUI as code
coverage. The properties are extracted from VCD. You need simulate only
once and you can then change your properties and re-extract coverage from
the VCD. They plan to add metrics for partial coverage of properties.
Synapticad now generates reactive testbenches with C++ instead of Perl.
They plan to support SystemC and SystemVerilog. They are moving toward
SCV (SystemC Verification language). They are doing more constrained
random vector generation.
Forte sells QuickBench, a testbench generation tool that uses
1. timing diagrams to define timing,
2. user created bus functional models, and
3. a program in the RAVE language to generate complex testbenches.
EDAptive Computing sells a tool that takes a high level system
description and test requirement in the Rosetta language and generates
tests. Currently the tests are C++; they are working on VHDL & Verilog.
Silicon Forest Research sells tools for automatic test bench generation,
but they were a bit fuzzy about exactly what the tools did. The input
is a C++ (not SystemC) high level description and a Verilog wrapper. It
creates PLI sequence generators that you use during simulation. They
claim a 5X improvement in verification productivity and say it's unlike
any other tool.
VeriEZ Solutions sells several openVera based tools, including a linter
and a tool that takes a list of modules and provides information on
hierarchy, etc.
Jeda Technologies sells the Jeda language, which was written by the
creator of Vera. They claim he learned from his first try and this one
is easier to learn and has cleaner assertions. It works with NC,
Modelsim and VCS, and whatever has PLI.
Avery Design sells a test environment for PCI variants, which includes
bus monitors, test suites and a functional coverage monitor.
Obsidian Software sells a tool to that creates random and directed random
assembly level tests for processors. They also sell versions aimed at
specific cores like MIPS and ARM, in case you are buying a core and
modifying it slightly. They say it takes a couple of months to bring up
a new microprocessor modeled in their Raven language.
- John Weiland of Intrinsix
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