( DAC 03 Item 7 ) ----------------------------------------------- [ 01/20/04 ]
Subject: Summit Visual Elite, Mentor HDL Designer (Renoir)
CAN YOU PICTURE THAT? Summit and Mentor Renoir are both old school graphical
design entry tools/companies. The one big change this year is that Summit
has jumped whole hog into being "the" SystemC graphical design entry company.
I guess they figure that SystemC is so ugly that chip designers would pay to
have a GUI to distance themselves from such an ugly hardware description
language. Is my Verilog RTL coding bias showing yet? :)
Design Entry
Summit was the original picture-to-code company. Typically beginners
loved the tool but once they learned the language they preferred to code
on their own. They moved up a level into SystemC modeling, which is
probably where a graphical tool is more at home... This year their tool
allows cores. They resell models for ARM, MIPS, and PowerPC integrated
into their environment. They also take C++ from Matlab, etc. Summit
emphasized how they can keep hardware and software in sync as each block
is pushed down to the RTL level.
Summit also has a code-to-pictures tool that can be mighty handy if
someone hands you three pages of code for a single state machine that
you've never seen before.
- John Weiland of Intrinsix
We have been using SystemC for about a year now from architectural
analysis, and refinement to RTL models. We synthesize from VHDL which
is hand-translated to and from SystemC. Evaluated Summit's Visual Elite
and Synopsys SystemStudio as well as OSCI on gcc.
We found that in SystemStudio the 'assisted' mode for generating SystemC
code is incomplete: often the tool inserts #error statements in the code
to indicate actions that need to be performed manually. Also, the
system rebuilds too much of the code for each run, slowing down the
edit-compile-run cycle.
Summit Visual Elite has a generally better user interface, successfully
hiding module and package implementation issues, leaving the user to do
the interesting bits. It also allows the user to escape the assisted
mode where this is wanted. Unfortunately it crashes a lot.
Even though we preferred the VE environment, we purchased Synopsys
CoCentric because of the availability of ready-to-run ARM processor
models and the stability problems of Visual Elite.
Now we use the free OSCI library more often than SystemStudio, as it
allows unlimited use of C++ features. Of course we do not get the easy
netlisting that the integrated tools support, but that is a very small
part of the design process anyway.
I would have liked to see the SystemC library more actively developed in
the community. Instead it looks like the SystemC development is still
being centrally done by a small group of people (probably inside one or
two EDA companies). The lack of a publicly accessible CVS tree or even
just regular updates (the last release was 18 months ago) is worrying,
suggesting that the SystemC project may fizzle out when the originators
decide to pull the plug.
- [ An Anon Engineer ]
In general, I am very satisfied with the Summit tool. It did everything
I asked it to. My design is fairly complex (~ 35K gate ASIC equivalent)
with some very stringent timing requirements and handshakes. I have now
concluded that SystemC is real... I did not do a whole lot of comparison
shopping before getting the SystemC license extension for Elite, since
we have been using Summit tools for about five years now.
- Mark De Spain of Sandia National Labs
I saw a small demo of Visual Elite this year at DAC. I'm mainly involved
in functionnal verification, but I keep a look a System Level Design.
I was a former unhappy Visual-HDL used (3 years ago). The main problem I
saw of Visual at this time was the way the database was stored
(impossible to access data in the directory). Moreover, we had some
problem (now fixed) of data loss.
Since Visual Elite integrates SystemC it seems to bring more added value
than just "Design Entry". Here are the notes I've taken at DAC :
PSL/Sugar support : not real. They just provide a interface to FOCS.
No analysis environment is provided nor debug features.
FastC is a subset of SystemC (cycle accurate level) for which they
provide an optimized simulator. They can however certify it is fully
compliant with the OSCI scheduler.
At least they will provide "native" support for HDL sources, i.e. it will
be possible to keep a given design hierarchy in a standard directory
structure. First will be supported for SystemC (Q4), then for
all HDL (Q104).
They don't work with Verisity, but are interested to do so.
- Olivier Haller of STmicroelectronics
I've been using intensively Summit's Visual Elite tool for the last
couple of years. I've recently completed the hardware design of a very
complex processor, which I'm planning to bring into the market very
soon. Visual Elite is a MUST in such complex system designs that have
to fit into an ASICs and/or several millions-gates FPGAs - in a timely
manner!
- Isaac Achler of iTOP
We have done an extensive comparison, involving head to head shoot outs
between Summit VE and Synopsys CoCentric. We obtained evaluation
licenses from each vendor and asked each vendor to build specific models
for us. We had 5 people and 3 projects on the job for about 60 days
(including 3 days of training from Summit and Synopsys). We have been
using VE , on the job, for about 4 months now . We've, consequentially,
purchased 2 VE licenses and 4 CoCentric licenses. Over the months, two
camps have formed. The Architects who favor VE for quick turn analysis
and the SOC guys who lean towards Synopsys for integration into the rest
of their tools.
We have contracted Summit to build more models and some tool
enhancements for us. All to be delivered on tight schedules. So far
they have preformed admirably with some little glitches.
We have detailed performance reports and a trade study but unfortunally
they are company propriety and it may be a complex task to clear them
for general release.
We find each tool has advantages depending on applications.
- Peter McShane of Northrop Grumman
As for Summit Visual Elite (not really a "C" only tool), we've used it
for Verilog generation for a few years now. I'd say it was a competent
tool, but it doesn't seem to have distinguished itself. As with a lot of
graphical tools, it tends to choke once you get up to the upper levels of
a design. I don't know how well it works with C, though.
- Thomas Fairbairn of 3com
Used Mentor's HDL Designer (Renoir) long ago. Noticed that things like
FSM designs didn't always generate the same RTL going from one version of
the tool to the next.
Hated spending so much time mousing around making the structural
schematics sheets look like something other than a rats nest. Now I use
the Opensource tool ChipVault for managing design hierarchy in both VHDL
and Verilog. I'm much more efficient and my designs can scale bigger
both in hierarchy depth and complexity without slowing me down.
- Kevin Hubbard of Siemens
We used to use Renoir/HDL Designer, but eventually dumped it. I've
always found graphical design entry tools to be more trouble than they're
worth. In a previous job, every so often a newbie designer would decide
to use such a tool, only to give up after a week or two and go back to
using a text editor like the rest of us. The rest of what HDL Designer
provides appears to be little more than an expensive GUI to what can be
achieved, on a Unix/Linux platform anyway, with free tools like 'make'
and RCS.
- [ An Anon Engineer ]
We use HDL Designer (Renoir) for all of our ASIC & FPGA designs. We
have about 40 engineers using it on a daily basis. We use the block
diagram (schematic) editor and a text editor, but we don't use the other
editors that are included (state diagram, flow chart). The big benefit
we see is the ability to more easily manage our designs. We use HDS'
integration with ClearCase for version management. Their integration
with ModelSim is great, but integration with other vendors' tools is not
as good (surprise).
It used to be somewhat slow when handling large design libraries, but
the latest release (2003.1) has vastly improved in its handling of large
designs and mostly text-based designs.
Some things Renoir is not so good at are VHDL specific features, such as
packages and VHDL configurations. Although, support for both are
steadily improving with each release.
We had evaluated Summit Design Visual HDL a few years ago (back when it
when it was Innoveda), but that seemed much more geared toward system-
level design. Also, their integration with ClearCase was somewhat weak.
- [ An Anon Engineer ]
Regarding Mentor's HDL Designer, to me it seems very good. I like being
able to create a block diagram for a design review, as I would in Visio,
and then click a button to generate the VDHL. The tool seems very
complete, containing integration capability for downstream tools. It is
fairly easy to discover how to work things, and the help screens and
tutorials are good. It will import VHDL and generate block diagrams,
which can be edited and made more readable. It seems that whatever you
might want to do, it can probably do it. It reveals a few bugs now and
then, but the Mentor online or phone support is excellent. Previously I
used Summit Design's VisualHDL, and Mentor's DesignView, but this seems
better.
- Doug Roberts of L-3com.com
In this particular design team we develop only FPGAs. We have two kinds
of HW designers: "Text Based" (VHDL written with Text editor) and "GUI
Based" (mixed text and design entry tool). Currently they are using HDL
Designer (Renoir) by Mentor.
Years ago we were Summit Visual-HDL users. Designers pointed out several
problems regarding Visual-HDL (i.e. daily crashes, heavy GUI,
unreliable...) In spite of our pressing requests, Summit did not
improve the behavior of Visual-HDL. Therefore, 3 years ago, after a
brief evaluation we decide drop Visual-HDL and use Renoir.
Our main decision points were block diagrams capture and VHDL netlist
generation quality, syntax and consistency checks and block diagrams
recovery. At that time we didn't examine features like flow chart and
truth table graphical editor.
Today we are using most of the features of Renoir with sufficient
satisfaction (i.e. export in HTML for Documentation, IBD, State Diagrams
Editor...in addition to the main features of VHDL import/export.)
Besides, with HDS 2003 (last version) we can deal more easily with big
FPGAs, e.g. Xilinx, Virtex II, and Altera Stratix. It was very
difficult with the 2002.x version.
Last but not least is DesignPad, the new text editor distributed
inside HDS series is a very useful tool but it still needs some
improvements.
- Massimo Ceppi of Siemens Mobile Communications
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