( DAC 03 Item 6 ) ----------------------------------------------- [ 01/20/04 ]
Subject: Forte Cynthesizer
THE FAVORITE BASTARD SON: Remember that earlier SystemC problem of being
only for architectural designers and NOT for practical gate-oriented chip
designers? Well, Forte Cynthesizer is the one company trying to fight that
problem by attempting to make SystemC synthesis practical. And since it's
SystemC, of course its behavioral synthesis we're talking about. That brings
its own additional baggage of the failed C-Level and Behavioral Compiler
tools, but if Forte can actually deliver real gates they might change some
skeptics views of SystemC. (But lets start seeing some real, verifiable
tape-outs here folks, before we start talking silly talk here.)
Forte Cynthesizer - Believe it or not, I have something nice to say
about SystemC! I attended a Forte behavioral synthesis demo with Brett
Cline, John Sanguinetti and other Forte engineers and came away
impressed. To me, the Forte guys said all the right things to a
SystemC skeptic like myself:
1. Forte was not promoting SystemC for RTL coding (smart move!)
2. Forte was promoting SystemC for behavioral synthesis (this made
sense to me).
3. Forte mentioned that behavioral SystemC ran very fast (I can
believe this and hope to try this out myself).
4. Forte tools translate behavioral SystemC to RTL SystemC and then
translates to Verilog RTL for synthesis (good choice).
5. Forte mentioned that their benchmarks showed that RTL SystemC ran
2X to 3X slower than RTL Verilog (very interesting data point).
6. Forte mostly used SystemC as I/O wrappers for other C-language
stylized behavioral synthesis code.
I came away with the impression that Forte is a top-notch Behavioral
Synthesis company that chose SystemC because it had established a
standard C-language hardware description style that Forte could
standardize on for tool interpretation. I hope to find time to look
over more of their demo software in the near future. I think these guys
are actually looking at SystemC from its strength--the behavioral
synthesis market.
- Cliff Cummings of Sunburst Design
I attended the Forte suite presentation at DAC, where they discussed
their SystemC behavioral synthesis product called Cynthesizer. My
impression is that Cynthesizer competes with Synopsys' SystemC
Compiler, but rumor has it that they are not developing that product
any longer.
I am quite impressed with the Cynthesizer demonstration, although I
haven't actually used the tool. Forte's basic premise is to be able to
take a high-level description written in SystemC (like our DSP models)
and automatically create multiple RTL implementations from a single
description. This would be good for us in that it allows architectural
exploration from a single SystemC model, allowing us to be able to pick
the best solution in terms of gate count, speed, etc. This could save
us a great deal of time and effort if it actually works. The strengths
seem to be the productivity gains and the high quality of results.
Forte's claim is that they are beating hand coded designs a high
percentage of the time. Even if they don't beat hand coded designs, we
could still use their results to pick an appropriate architecture /
design approach for the application at hand.
The downsides seem to be that it there is no formal verification to
check the output with the original SystemC, and it seems to be
optimized for ASICs rather than FPGAs. Also, it only supports Verilog
and SystemC output (not VHDL currently). Additionally, it doesn't give
you any type of power consumption estimate. This could be very handy
in our work, as it is a major requirement for our products.
- Bill Dittenhofer of Starkey
Behavioral Synthesis overall -- each behavioral synthesis tool has a
lack of verification capability. I believe SystemC and/or System
Verilog to RTL is a good direction in future technology. But these
behavioral design environment require both synthesis and verification.
The verification needed is:
- Equivalence checker between SystemC/System Verilog and generated RTL
- Stoical robustness check as assertion based verification tool in
SystemC level. It is fine if other EDA venders will support this
capability.
Forte's SystemC Cynthesizer -- Forte's Cynthesizer behavioral synthesis
tool generates several candidate RTLs, which is much better than their
competitors' offering. Also, it looks like Forte makes it easy to
select these candidate architectures. However, Forte still does not
have verification capability. If the RTL generated has some bug or
some tight timing constraint or some requirement to modify the RTL, it
is very hard to implement each candidate RTL to gates.
If Forte will establish design flow including RTL robustness
verification, it will be major design methodology.
- Yutaka Koike of Oki Semiconductor
Forte's Cynthesizer is a good-looking behavioral synthesis tool. It
seems to have a good flow to go from "C" code to Verilog. It remains
to be seen how good the Verilog code is that it produces. I have the
idea that most hardware designers are not ready to use some of the "C"
like tools.
- [ An Anon Engineer ]
I saw Forte's Cynthesizer demo at DAC in June (we haven't use the tool
yet). Their behavioral synthesis tool feature set seems to be very
capable. Forte's C synthesizer accepts C++ and SystemC code. The tool
has a testbench that allows the designer to do co-simulation (running
software code on the hardware model) therefore producing a functionally
correct hw model. Once this model is correct, it gets synthesized into
RTL.
I believe it's a matter of time for everybody to move up to a higher
level of abstraction. If we look at history, we've gone from
layout->gate->RTL. Every time we moved, there was skepticism and
procrastination. We've already seen these behaviors.
In addition to Forte, I saw Future DA and Y-Exploration tools. Both
synthesize C++ into RTL. They seem too small ventures. Forte has a
better support model.
- Rene Delgado of Motorola
We have used SystemC in transition level modeling for two years, which
has enabled early software development as well as system performance
analysis. The SystemC models were used as the reference model for the
hardware Verilog modeling.
We have been waiting for a tool from the EDA industry for the top down
"refinement" approach using SystemC. Instead of starting the SystemC
and Verilog in both ends and comparing results, the ideal solution
would be to start with SystemC in transition level modeling, refine in
hardware functional modeling, refine into synthesizable modeling, then
RTL and gate level.
Cynthesizer from Forte addresses the problem from synthesizable
modeling from SystemC to RTL. Although the synthesizable modeling
subset in the SystemC standard community is still under discussion, we
are looking forward to trying out Cynthesizer.
- [ An Anon Engineer ]
Forte told us about their Cynthesizer behavioral synthesis product. I
had looked at it about a year ago in regard to another project and I
was very pleased to see the progress they have made. This is exactly
the kind of tool we need to manage our fixed function block design flow
for a family of product SOCs we have in the works.
In a world overly cluttered with poorly conceived design tools and
flows, Forte's Cynthesizer is a beacon of rationality!
- Dave Baker of SigmaTel
I saw a demonstration of Forte's Cynthesizer product, which is a
behavioral synthesis system that takes C++/SystemC in and produces RTL
out. The demo I saw used C++ only, but they said that SystemC was also
supported.
Basically Cynthesizer is a behavioral synthesis system in the
traditional sense with a few bells and whistles to make it more usable.
The designer specifies the algorithm in a mostly untimed fashion plus
constraints on cycle time, and Cynthesizer produces an RTL
implementation for it. I have worked for many years in the field
(including developing 2 industrial strength behavioral synthesis
systems, and I don't work for Synopsys) and to me the Forte Cynthesizer
looked good, but not significantly different from what has been
done before.
Part of the problem with behavioral synthesis, which designers dislike,
is the change in timing (cycle-by-cycle) behavior that is introduced by
behavioral synthesis algorithms. In other words, the behavioral
specification is mostly untimed from a cycle-by-cycle point of view,
but the RTL implementation obviously has cycles. This makes it very
difficult to use the same testbenches before and after.
I mentioned this to Forte and their answer was that, they have
addressed the problem by requiring the designer to "structure" his/her
behavioral description in 3 blocks. The initial block represents the
data input part, and it should have explicit cycles by means of "wait
on clock" statements and thus has a fixed cycle-by-cycle behavior. The
middle block contains the computational/algorithmic part and does not
need a fixed cycle behavior. Cynthesizer will scheduled this middle
block to meet the constraints. The 3rd block represents the data output
part, and again contains "wait on clock" statements to fix the cycle
behavior. Since the input and output behaviors are fixed by the
designer (as far a the cycle behavior goes) the same testbench can be
used in the behavioral and RTL descriptions. This is not a new idea and
users of behavioral synthesis (yes, there are a few) have used this
trick for a long time. This helps but it does not solve the problem. If
you have a design that has to interact with the environment quite a
lot, during the computation part, this solution does not work well,
because you end up having to constraint (i.e., add "wait on clock"
statements) also inside the algorithmic part which limits the
exploration space for the behavioral synthesis algorithms.
All in all, the tool Cynthesizer looks good as a behavioral synthesis
tool, but it has not fully addressed many of the methodology problems
that have plagued behavioral synthesis. Still for some niche markets,
it will probably work well.
As a last comment, I would like to point out to you that several
companies at DAC were showing products which used behavioral synthesis
algorithms under the covers, but they were not calling it that.
- [ An Anon Engineer ]
I was intrigued by Forte's SystemC synthesis demo. We saw a
Cynthesizer demo in the Booth at DAC, and later had a private demo.
The capability of going from SystemC to RTL is a technology that we
currently are interested in exploring. The Forte SystemC synthesis
product will open doors for us that will allow us to try out high level
"C" based algorithms and quickly prototype hardware in FPGA's.
- Paolo Masini of Raytheon
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