( DAC 02 Item 25 ) ---------------------------------------------- [ 9/10/02 ]
Subject: Prolific, Cadabra, Circuit Semantics, Silicon Metrics, Zenasis
FOURSOME, ANYONE?: Other than Numerical buying Cadabra, it appears that
the old pairings still apply here. Prolific users tend to use it with
Circuit Semantics. Cadabra users tend to use it with Silicon Metrics.
I guess some thing never change.
"26.0 Library Generation and Characterization
Prolific sells layout generators for standard cells, basically going
from a desired SPICE netlist to GDSII. They use multiple small
generators for larger cells (e.g. 3 or 4 for a flip flop) and then do
compaction at the end. This allows easier creation of new generators
by the user. They can produce cells for 90 nanometer IBM and TSMC
processes.
Cadabra is owned by Numerical Technologies and also makes layout tools
for standard cells. The salesman was nice enough to compare and
contrast with Prolific. He claimed Prolific relies on generators,
which take some time and skill to set up (usually a lot of AE hand
holding) but then once it's set up it spits out new cells in the blink
of an eye. The Cadabra salesman says their tool does actual place and
route rather than generation, followed by 2D compaction (versus 1D+1D
for Prolific). This means less setup than Prolific, longer run times,
but probably a more space efficient library.
The SPICE-like analysis tools from Siliconcraft can actually modify
your netlist to optimize for speed and power. It does this by creating
additional cells in your library (possibly hundreds of them) with
different drive strengths. It interfaces to Cadabra for layout.
Silicon Metrics also sells library characterization software. They
sell tools to do memory characterization, to I/O characterization, and
to do critical path characterization (like SPICE running within
Primetime). The can output to the ELF or the new SPDM (new Synopsys
.lib format). The salesman said the OLA library format just wasn't
taking off. They are also working on their own standard glitch format.
They are (or were) teamed with Sequence Design somehow in the power
arena.
Library Technologies also sells library characterization software.
They take the cell function and a seed netlist and produce library data
in a variety of formats, including the new SPDM Synopsys format. I
believe they can also size cells to create new cells on the fly to
solve problems (but I think some other tool has to produce the layout).
They can generate glitch propagation information and plan to do that in
the new Synopsys format.
Circuit Semantics sells tools to characterize cells or larger blocks,
which includes some sort of transistor level static timing analyzer and
a tool that can algorithmically extract the Verilog function of a SPICE
netlist (Innologic may have something similar).
Zenasis Technologies accepts Primetime commands and create custom sized
cells to optimize your timing. It produces a cell SPICE netlist, which
can be implemented using something like Cadabra.
Legend Design Automation sells a tool for memory characterization that
they say is like HSPICE but 2X-10X faster."
- John Weiland of Intrinsix
"Prolific and Sagantec stand out. Silicon Metrics is rediscovering
itself. Numerical/Cadabra have some market share and brand. The
other guys are not going to get any major chunk anytime soon."
- Jai Durgam of SiImage
"We are using Silicon Metrics and Numerical/Cadabra. I think Apache is
very interesting. We might benchmark the tool."
- Zenji Oka of Ricoh
"One year after Cadabra released "Abracad", Cadabra made a lot of
improvements after customer feedback and bug fixing. The tool is now
stable. The positive Abracad points I've found:
1. The design rule/architecture setup is under a GUI. In the
previous version of Cadabra's "ClassicSC", the setup was done
using "AL" code, which is C++ type OOP code with pre-define
classes. I was comfortable with AL coding, but this GUI setup
environment made the life much easier. If you want to do some
fancy "AL" coding, you can still do it.
2. From Cadabra, you can get rapid startups. So for most foundry
process technologies, you do not need to read through boring
design rules, and try to enter all values one by one. From the
Abracad GUI, you can configure most popular architectures easily.
3. It's cell layout is very good quality. I can say that the layout
is as good as manual layout, and in some cases it is better than
manual layout. Reason: manual layout usually only goes through
1 transistor placement/routing, while Abracad can branches all
different placement/routing, and then select the best one.
4. Abracad runs in fast Linux machines. I did a few libraries with
3-4 licenses. I could finish one library within 2 weeks by
myself, which is un-thinkable for manual layout implementation.
5. The tool supports process migration. If you migrate from similar
process in similar architecture, eg: from TSMC 0.18 um to TSMC
0.13 um, it only takes a couple of days, and with a 98% success
rate. Little manual editing is needed. Also, you can migrate
from cell GDSII directly.
6. It comes with pre-defined macros. For example: the macro ATL will
takes cell netlist and go through place, routing, compaction and
output GDSII automatically.
7. You can patch an almost-done library if you want to add more
improvement without starting from scratch again.
The negative Abracad points I've found:
1. The tool is not cheap, which makes impossible for some companies
to own if they just want to do one library per year.
2. The "AL" coding just scares away a lot of layout engineers,
since those people are not familiar with coding, while more
comfortable with a manual interface.
3. There are some poly jumpers in some layouts, which is bad.
You have to find these and fix them manually.
4. Some shapes can be simpler and better, eg. the line can be
straight, and does not need to be "z" shape.
I am very familiar with Abracad, and even used beta version of it. I
evaluated a lot of tools, and I like Abracad most."
- Yingming Lou of Zenasis
"I chose Cadabra as a cell layout tool in order to reduce design time
and to get reliability/homogeneity *without* depending on an
individual designer's personal ability. We have applied Cadabra to
our 0.8 um to 0.10 um cell libraries. The usage of Cadabra goes up
to 80% of whole cells. The rest 20% of cells have more than 50 Trs.
and are handcrafted because of less capability of compaction.
In Cadabra the layout engine and architecture are separated. This
means that one user can control the sequence of layout & programming.
The average layout time needed was about 50% of hand crafting (with
time needed for creating the environment) but that comes to down to
30% (with complete technology files.
We had to perform "cut & try" jobs so much. The concept of "cost" is
very hard to understand because we couldn't recognize the difference
between "30 > 20" and "20 > 10", for example.
The advantages of Cadabra are price, ease of use and preformance of
compaction. Once we tried Cadabra, we couldn't go back to Prolific."
- Etsuji Yoneno of Soliton
"I think that Silicon Metrics SiliconSmart CR is a great tool because
it provides accurate cell characterization and modeling while also
being flexible and easy to use. Silicon Metrics provides first class
support for their tools. I have genuinely enjoyed working with them."
- Jennifer Richards of Fairchild Semiconductor
"The Silicon Metrics guys have a bunch of new characterization tools.
They are a fairly simulator engine independent, so guys with in-house
branded tools can still use them. I like their trend of higher and
higher functionality be handled - they started with std cells, then
went to memories and now I/O. Once Silicon Metrics does datapath,
they will have the whole custom block characterization wrapped up.
Unlike the CSI products, theirs is a good down market product. It
actually requires less staff to support a design with Silicon Metrics
tools in the flow and they give a schedule reduction rather than
increased/same staff and a schedule extension. I also did not see
anybody else offering SPDM models (if these actually take off) they
are in good position."
- Pallab Chatterjee of SiliconMap
"Circuit Semantics is little more mature in term of extraction from
SPICE. Still some way to go to for full maturity. They are able to
provide timing characterisation, Verilog model, and .lib format."
- William Lam of Tvia
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