( DAC 02 Item 21 ) ---------------------------------------------- [ 9/10/02 ]
Subject: Simplex, Apache, PrimeTime-SI, Iota, Celestry, EPIC
POWER, NOISE, & IR DROP: Again more acquistions happened here with Cadence
gobbling up Simplex and the unexpected purchase of Iota power tools by the
FPGA synthesis leader, Synplicity. Synopsys has joined the noise & cross
cap game, by adding SI to it's popular PrimeTime STA tool. The interesting
new kid here, again, is Apache Design Automation with their Tomohawk tool
that does IR/EM analysis. A number of observers noticed Apache here.
"I heard promising things about Simplex. Still not using Synopsys
PrimeTime-SI."
- Pascal Gouedo of STMicroelectronics
"We've found Celestry, Avanti Star, PrimeTime-SI all useful. We tried
Simplex and we're not happy with it and will discontinue using it."
- [ An Anon Engineer ]
"We use and plan to stick with EPIC Arcadia and PrimeTime. May add
PrimeTime-SI soon, but haven't felt the pain yet."
- Mark Wroblewski of Cirrus Logic
"14.0 Static Timing Analysis & Delay Calculators
The 800 pound gorilla here is Synopsys PrimeTime, which owns the
majority of this market.
Cadence has been talking about nuking Pearl for more than a year now.
I heard that many custom logic designers use Pearl because it can
handle transparent cells (like domino logic) that Primetime cannot.
Simplex (Cadence) sells SignalStorm, a delay calculator which they say
is 4X to 20X faster than Primetime but can actually include effects
of IR drop and crosstalk, and can understand grid structures, and will
feed Primetime the delays so you can analyze your paths there. They
claim delays are within 2% of SPICE.
Celestry sells their Nautilus DC delay calculator. They say it can
handle huge RC databases and do 2D and 3D meshes, parallel drivers, and
all sorts of other nasties, plus can provide a SPICE netlist of your
critical path and a graphical analysis of the clock skew across the
chip. Their Nautilus VT tool also takes into account IR drop and hot
spots.
Sequence Design sells a static timing analyzer that takes into account
crosstalk problems (both delay and glitch problems).
Incentia sells a static timing analysis tool that they say is at least
an order of magnitude faster than Primetime, completely compatible with
it and much cheaper. They now have a few tapeouts under their belts
and the salesman seemed genuinely perplexed as to why it wasn't
selling better.
Circuit Semantics sells an STA tool that can combine SPICE and gate
level analysis, and seems aimed at designs that mix ASIC and full
custom design techniques."
- John Weiland of Intrinsix
"Simplex too expensive. Signal Integrity tools all lack in some
features and are being promoted/marketed wrongly/inaccurately. Same
with noise analysis tools. Celestry is probably going to go away.
They have been late to market with all of their products."
- Jai Durgam of SiImage
"Just started using VoltageStorm. Looks good but I don't believe the
quantative results. Showed a 0.5 V drop in one section of my chip and
0 everywhere else. Didn't really make sense. I see clock tree
synthesis being a major problem going forward (or deeper sub-micron).
Capacitance (i.e. cross-cap) has a big effect on cell delay, so can't
predict clock tree delays without doing a detail route. So Celestry
isn't as useful as it seems, because we won't get those delays in
reality and still have to go back and fix holds."
- John Webster of Intel
"19.0 IR Drop Analysis
Simplex claims their VoltageStorm tool now controls 75% of the market.
The EPIC Railmill tool, owned by Synopsys, is still around but there
isn't much talk about them any more. The algorithms just won't work
on today's chip sizes.
Nassda has a bunch of ex-EPIC people. They have introduced their
Lexsim tool, which does hierarchical IR drop analysis (giving faster
simulation) and has built-in algorithms for reducing the huge databases
of extracted parasitics. They claim this is the first tool that does
direct analysis of dynamic IR drop (don't know exactly what that means
versus Simplex, Epic, etc.)
Celestry sells Nautilus VT, which analyzes for IR drop, hot spots and
potential electromigration and outputs not just a report of problem
areas but also delays for your static timing analyzer.
Celestry also sells Nautilus SI, which does signal integrity analysis
and seems designed to be coupled with their other Nautilus tools. I
know it looks for delay problems but I'm not sure about glitches."
- John Weiland of Intrinsix
"PrimeTime-SI we will start to eval eventually. We are also trying to
get our backend folks to look into Avanti Starsim-XT to extract clock
nets, since their current method is terrible and produces hard-to-meet
constraints in STA.
Our backend guys use Simplex VoltageStorm to measure IR drop and (I
think) to do EM checks. Right now it doesn't do EM checking on clock
nets though!! (only VDD/VSS). The IR drop seems to work well, it
found some missing power straps. Runs slow though (1-2 days for VDD,
1-2 days for VSS)."
- [ An Anon Engineer ]
"Used PrimeTime-SI on some designs. For our designs it was adequate but
we are not really pushing the envelope wrt SI issues."
- Phil Hoppes of Intersil
"Simplex is good with some minor bugs. I am not sure today anyone has
a tool which catches all glitches."
- Mehran Bagheri of Multilink Technology
"20.0 Power Tools
EPIC (owned by Synopsys) sells Powermill, but it's awfully slow on a
big chip.
Nassda has a bunch of ex-EPIC people and sell HSIM, which competes
against Powermill. They say the fact that is retains hierarchy means
it simulates much faster than other technologies.
Simplex's Powermeter is a vector independent pre-layout tool; it uses
activity level and dominant logic state like Synopsys Design Power,
which requires some guesstimation."
- John Weiland of Intrinsix
"We used Apache very successfully to analyze two very large 0.13 um
ASICs and were pleased with the results since they did find areas
of EM violations. We are flip chip so IR is not so much of an issue
for us. (One of the layout guys here actually ran Apache on the
chips.)
I personally am not familiar with their vectorless EM/IR approach.
We used estimated switching factors of 25% to do our analysis. I
prefer a vector based approach that the Sente tool uses. My
experience has been that estimated switching factors tend to
overestimate the actual currents and so make us do more work.
They are inherently inaccurate.
That all said, Apache was very fast and has a very good debugger
unlike Simplex or Iota (which we also tried to use). Apache is
also much easier to use than the other tools. We compared Simplex
and Apache runtimes. Simplex was 8 hours and Apache was 1/2 hour.
Because I was the chip leader for both chips I was very pleased
that Apache found these problems *before* tapeout."
- Sudhanshu Jain of Broadcom
"Compared to Simplex, Apache was easier to use and had sufficient
accuracy at earlier stages of design for us to get a head-start
with power grids on our design. Based on their analysis, we
doubled our power grid metals and still ended up barely meeting
the final IR-drop requirements. Without that warning, the design
(or at least our schedule) would have been a disaster."
- Charles Ling of Mindspeed
"In our comparison between Simplex, Iota, & Apache, we found that all
the tools yield simular results. It's run time and memory usage where
we found differences. From a 2.5 million instance real design run:
Simplex completed in 290 min with 3.1 GB memory
setup:
abstract for XGXS, DEF for core hierarchical blocks,
even power distribution among mesh assumed
Iota completed in 405 min with 3.8 GB memory
setup:
abstract for XGXS, DEF for core hierarchical blocks,
even power distribution among mesh assumed
(m2-5 removed from XGXS abstract for Iota to run successfully)
Apache completed in 33 min with 1.6 GB of memory
setup:
DEF for top, core hierarchical blocks, & XGXS
full hierarchy analysis
Power number for all cases were from synopsys .lib files. XGXS power
from our library group.
Ease of Use: (easiest to hardest)
1. Apache/Iota
2. Simplex
Preference:
1. Apache
2. Iota
3. Simplex*
Note: * -- very distant 3rd.
Apache completes hierarchical IR/EM analysis in one step. It does not
require abstract generation for blocks followed by a top-level run like
Simplex. It reads GDS for the memories and distributes power across
all transistors in the memory with a decent estimate for where current
is being sunk. It handles metal fill data with little impact on
runtime or memory. The other 2 tools choke with this large amount of
additional data like this."
- [ An Anon Engineer ]
"Although I have yet to actually run a test case through the Apache
flow, from watching their canned demo at DAC it seemed that the user
interface of inserting a design into their flow is straight forward
and very clean. Also, it is much easier than the process necessary
for running a Simplex power analysis. Apache appeared to have
sufficient capacity and performance in that a reasonably sized design
finished its analysis in the time it took for their presentation (not
a big suprise).
I think it is a great idea to add inductance and bypass caps to the
power analysis so that you are not suprised by what silicon shows you.
Also, their vectorless approach is novel. We have been using bypass
caps for years but have not had the tools necessary to show the exact
benefit they provide.
The main problem with Apache is that it is a point tool and from my
view it is essentially an analysis tool. Although it may indicate
there is an issue, the means for providing a fix to the issue is not
integrated with the tools we are using. To a large degree, bypass cap
insertion requires space to be available. Many times it is very
congested at the location where it is needed the most. Therefore, I
believe Apache is capable of highlighting potential issues in a design,
but the same problem may potentially be solved indirectly through a
methodology of targetting lower utilizations in designs so that more
area is reserved for bypass caps as a rule and not an exception."
- Brian Arnold of Vitesse Semiconductor
"We worked with Apache on Tomahawk tool evaluation on their site. We
provided a block as a test case and found:
- Accurate power measurement based on static activity number
or dynamic vectors.
- Static and dynamic switching activity capability.
- IR measurements are done and reported on a map of DEF.
- Accurate reporting of EM violations (coordinates on DEF)
- Finds via deficiency in P&R design (no tool currently
available has that capability).
The only lowlight is lack of documentation at the time of evaluation.
We think Tomahawk is good for EM, IR and power analysis for big chips."
- Larry Chau of Infineon
"There is a company called Apache Design Solution that does 'dynamic'
analysis on power and SI with large capacity."
- [ An Anon Engineer ]
"We looked at Apache, Simplex and Avanti. Did not look at Iota.
On Day 1 we tested Apache on a small module (~4K unique instances).
It took standard LEF/DEF, .lib and foundry tech files to run the tool
(Tomahawk). It took about 45 minutes to complete EM/IR analysis on
their laptop running Linux. We were impressed with the capacity, run
time and ease of use of the tool. Tomahawk provides both static and
dynamic modes for voltage-drop/EM simulation and analysis.
It comes with a circuit simulation engine, which can simulate R,C and L
circuits, perform RC tree reduction, and using a new algorithm, solve
a complex network with inductance. We used the static mode to do the
quick filtering then we enabled dynamic mode to perform detailed
analysis. The two mode approach helps to narrow down the search spaces
and pin point the real problems.
Tomahawk flagged our EM/IR problems on our block where we only had two
small power rails because we had not included the upper level power
grids. The tool has a 'virtual exploration' feature to allow the user
to easily try what-if scenarios.
A nice feature of Tomahawk is auto-insertion of decoupling capacitors,
which we require for our designs. It calculates the required cap and
can place them where they are needed. Their GUI gives you quick visual
feedback on decap placement."
- [ An Anon Engineer ]
"Signal integrity has entered into an era of more refined accuracy with
the support from library characterization vendors. Power and power net
related issues becomes the next target in SI which the new start-up
Apache seems to be focusing on."
- Weikai Sun of Volterra
"In our test case, Apache did the power analysis, voltage drop and EM
analysis for our chip using Tomahawk. The chip is a VoIP chip, 0.18 um
1P6M technology, 500 K instances, and speed is 133 MHz. We gave
Apache LEF, DEF, DSPF and VCD file. After they did the preparation
work, they brought a notebook (1.8 GHz, P4, Linux) and ran the whole
chip here at our company. It finished in around 15 minutes. I also
ran Astro Rail for the same chip.
Apache Tomahawk
---------------
1. Total power: 1.79W based on 0.2 toggle rate.
1.678W based on VCD file.
run time: 15 minutes
2. Voltage drop: the worst is 4% of VDD which location is matched
with what Astro reported.
3. EM: no violation at 80 C. 473 violations at 125 C. The worst
location is different from Astro's report. I didn't check the
rest of the locations.
Avanti Astro Rail
-----------------
Run on Sun Blade 1000, 4G memory, Solaris.
1. Total Power: 1.748W based on 0.2 toggle rate.
1.575W based on VCD file.
run time: 70 minutes.
2. Voltage drop: the worst is 8% of VDD.
run time: 30 minutes.
3. EM: 25 violations at 80 oC.
The flow for the Astro is not quite easy. It took a few days to figure
out the flow and do the preparation work. I am not sure how Tomahawk's
usage was because it was done by Apache. My impression of Tomahawk is
it's very quick and accurate, the power and voltage drop reports are
matched with Astro. It's a good tool to put in the design flow to do
a quick analysis and save the turn-around time."
- Ri-De Wang of Ishoni Networks
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