( DAC 02 Item 17 ) ---------------------------------------------- [ 9/10/02 ]
Subject: InTime, Icinergy, AmmoCore, Tera Systems TeraForm
MUTATING TO SURVIVE: Two years ago design estimators sort of cautiously
tested the concept of their tools at DAC '00. This year, in order to
survive in the current unforgiving business environment, InTime, Icinergy,
and AmmoCore have recast themselves as floorplanning/partitioning tools.
Tera Systems is the only estimator that has remained as an estimator.
"They divide into 3 subcategories:
A) Estimation/planning tools working on RTL or higher level:
InTime's Time Builder, Icinergy SOCarchitect, Tera's TeraForm.
B) Planning/partition tools working on gate-level:
Cadence (SPC) First Encounter, Monterey Aristo IC Wizard,
Monterey Sonar, Synopsys Floorplan Compiler, Magma Blast Prototype.
C) AmmoCore Fabrix
This is a category of its own. Can be roughly categorized as a
"tool capacity amplifier". At this time works only with Cadence
backend and dedicated hardware for multi-processing.
Tera System is the leader in category A).
SPC is the leader in category B). However, the automatic partition
concept was brought in by IC Wizard, and the other tools (Synopsys,
Magma) seem to follow this concept. Sonar and IC Wizard should be
really considered as one tool.
Not sure whether the concept C) will take on and whether we see more
tools like AmmoCore. Has a strong potential, if it can be made to
work on any platform and with any backend."
- [ An Anon Engineer ]
"I am indeed a user of the Icinergy SOCarchitect tool. I started using
the tool after PMC-Sierra bought the company I was working for (Extreme
Packet Devices). PMC was introducing the tool as a preliminary
floorplanning exercise tool and we were able to put it to good use in
that area.
While at EPD, I used Synopsys' Chip Architect to floorplan a 1 million
gate networking chip which we were doing with NEC. It was a wirebond
die with about 4Meg of SRAM in about 40 instances, over 300 signal I/O
and running at 150 MHz in .18u. As you can imagine, you really need to
do some good up-front floorplanning on a chip like this to ensure you
can achieve timing closure when bussing wide data signals around the
SRAMs, to and from the I/Os and between major functional blocks.
We found we had quite a time just getting the design imported in to
Chip Architect, and required extensive on-site support from Synopsys.
The problems were mainly with data-base format differences between what
we were getting from NEC and what Synopsys expected. We did manage to
get an initial floorplan done using Chip Architect, but ended up
switching to the NEC in-house floorplanner for future revisions.
After PMC purchased EPD, the task was to retarget the ASIC to PMC's own
process. This of course meant a different library, changes in SRAM
configurations/areas/aspect-ratios and different I/O placement. We
used SOCarchitect right from the get-go to understand the feasibility.
The power of the tool here is that you don't need to have any sort of
LEF/DEF/netlist to get going. A simple estimate of gate area for a
given density, and area + aspect ratios for your SRAMs (or any other
hard macros) is enough to start putting the puzzle together. You don't
need to worry at all about database compatibility at this stage and you
can get a good picture of whether you need to make any immediate
architectural changes (although if you do have physical models of the
macros -- say LEFs -- it is really nice to be able to read them in
and see the pin placement to get a good idea of the best orientation).
At this point you can plan your regioning or physical hierarchy as best
suits your macro placements. Once you get what you believe to be a
good floorplan, it is a simple matter to print out an Acrobat PDF for
review by your physical designers.
When I started at Tropic, the architecture of the chips they were doing
was still in flux. I immediately requisitioned a copy of SOCarchitect
and began floorplanning the various alternatives. Right away we were
able to throw out the ideas that were physically not feasible and focus
in on the ones that might work. Again, at this point there was no RTL
written and no physical libraries available. We were working with gate
and die size estimates and SRAM/macro data sheets, just entering the
raw data into SOCarchitect and moving things around. We were also
comparing the possible solutions in 2 different vendor's technologies,
so we were able to select the best vendor, while flushing out the most
viable architecture.
For me, the power of the SOCarchitect tool is this ability to get to
work very early on during the architectural planning: What are the
size/configuration constraints for your tables and other storage on
die? How many other macros are feasible? How should you define your
placement regions or physical heirarchy? Where are your critical I/Os
with respect to the logic that drives them? In fact, I've never used
any of the more advanced features of the tool such as reading in a
netlist or writing out a PDEF. I've suggested that Icinergy needs to
release a "lite" version of the tool that has only the subset of
features (the ones that I use of course) at a much discounted cost.
My main complaint being that I can't justify spending $20K on the full
version of the tool when I only use the basic features and only for
the first part of the design cycle. We are an ASIC shop and the
detailed floorplanning is done by our vendor. So far I haven't seen
any plans for a lite version but I keep asking. On the other hand,
the company has been very responsive in listening to our comments and
adding requested enhancements and capabilities to the tool. I often
recommend the tool to colleagues and would love to see some of the
ASIC vendors out there pick it up as part of their tool-kit offerings."
- Jeff Romanko of Tropic Networks
"Icincergy's SOCarchitect looks very useful as a floorplanning tool for
system architects & frontend designers (i.e. pre-layout people)."
- [ An Anon Engineer ]
"To some extent Icinergy's SOCarchitect is still a work in progress, but
I think there's enough there already for genuine project benefit. You
can use SOCarchitect to start floorplanning from the conceptual stage.
You can use that floorplan to steer synthesis and placement tools as
you implement your design. You can use the results from synthesis and
layout to iteratively refine the floorplan all the way up to tape-out,
in order to balance congestion, utilization, and timing across blocks.
The cost of SOCarchitect is cheap enough that it can be considered for
use as a team tool, without artificial distinctions between pre-RTL,
RTL, and gate-level phases of your project.
I consider pad ring placement, hard macro placement, and power grid
implementation to be part of floorplanning tool territory. In the
current release, SOCarchitect's power planning capabilities are quite
minimal. Icinergy says that that's a priority focus area for them; I
can't speak to how long it'll take them to deliver this. For now,
serious power planning really has to be done outside of SOCarchitect
and the results imported into the tool.
The focus of SOCarchitect is somewhat narrower than that of First
Encounter, which I put at the top of the pack right now. But
First Encounter costs significantly more than SOCarchitect, and it
has a significant functional overlap with other existing mainstream
design tools. So while Icinergy's SOCarchitect doesn't perform
detailed gate placement or clocktree generation, I think it's quite
acceptable to simply use the existing alternatives (PhysOpt, ClockTree
Compiler, Silicon Ensemble, etc.) for those tasks. The core benefits
that I'm looking for can be obtained using a *combination* of tools.
Now that Cadence owns First Encounter it'll be interesting to see if
they bundle it so tightly with other Cadence tools that they may
eliminate First Encounter as a plausible choice for anyone who isn't
using a Cadence-only design flow. If Cadence winds up making that
easy mistake, or if they emphasize marketing over continued technology
development within First Encounter, then it'll help clear the field
for tools like Icinergy's SOCarchitect."
- Mike Carter of Idirect
"Some of these floorplanning tools probably pay off for large designs
but for us doing 2-3M gate designs, not much value. Winners: SPC,
Magma. All the other guys are going to have to fight for some small
market share but aren't going to make the headlines. InTime seems
to have grown significantly in 2 years (the founders are probably
the best known in the EDA world anyway) but with both Cadence and
Synopsys (especially with Avanti) selling integrated solutions as
well as Magma, makes me wonder..."
- Jai Durgam of SiImage
"AmmoCore sells a floorplanner and placer but no router. Their tool
starts with a gate level netlist, does automatic floorplanning, timing
driven partitioning and placement and static timing analysis. Their
STA accepts SDC or GCF and they say it correlates well with Primetime.
Their placer chops the design into small pieces and allows dozens of
processors to work on it. I'd be interested to see how efficiently
this can be done."
- John Weiland of Intrinsix
"AmmoCore is more than just an estimator/floorplanner if you had gone to
the demo suite. It looks too good to be true to claim "No design is
too big". Their one engineer / one flat chip / sblock approach may be
comparable to that of IBM. It was able to take a netlist, do place,
CTS, route, and SI analyze in the demo.
If Ammocore makets properly it might blow away hiearchical approach and
niche tools with small capacity.
Cadence's First Encounter is under some integration pain; it has no
power route for pre-placement power analysis; still lots of work to
do to make FE/Nanoroute work together - lots of bugs!!
Synopsys Floorplan Compiler (the awakened Hidden Dragon??) will need
to erase the not-so-good impression from Chip Architect. Magma's
Prototype is a plus that adds on to BlastFusion and backed by Diamond
SI for backend check. Magma so far has the most integrated image out
of all EDA companies."
- [ An Anon Engineer ]
"We are early adopters of Ammocores Fabrix and are currently running it
on a real customer design. This tool has very impressive performance
in terms of TAT. We are sorting out some usual issues that a new tool
normally has, as this would be is their first tapeout design, I guess."
- Thomas Langfermann of NEC Europe GmbH
"I have used InTime's Time Architect for about 6 months now. Mainly I
am using it to estimate silicon area, architectural trade-offs, and
technology trade-offs for my design proposals and what-if analysis.
I find Time Architect very easy to use. Its Client/Server web
capability works well to conveniently generate the needed proposed
information for my customers. It also provides enough control points
which allow me to adequately tune the the accuracy of its estimation.
I also like its report generation feature, nothing rocket science
here, but definitely a time saving feature when I work on a proposal
or documentation.
Time Architect currently does not automatically extract sufficient
technology and library information it needs from an industry standard
form. Some manual effort is usually necessary. This makes the
process of adding a new library to the system a little painful and
time consuming. I hear inTime is currently working on this and has
the beginnings of an automated setup, but I have not had a chance
to try it out yet."
- Hung Hua of Signet
"InTime vs Synopsys/Cadence/Magma
There were four key features of the InTime product offering that
appeared to be unique in providing a solution that the other
players were missing.
First, for designs that have a high degree of fixed cells - large
memory content, large processor core - most of the other
floorplanner/partitioners have a lot of difficulty over about
60% hard obstructions. The InTime Time Architect product uses
multiple algorithms for solving the initial placement and
estimation problem, so the porosity of the design is not an issue.
It has been a standard workaround that if you have an area of high
fixed device area - that you do a 2 step process to connect:
1.) first you build a "dummy" holding area for the new gates
in the gap between the hard macros and fix placement,
2.) then you route the resulting blocks on a top level stitch basis.
This is a real pain in the neck for some designs where is it not
possible to "logically" group this interconnect logic into a single
RTL module and still maintain testability of the design. The InTime
products (Time Architect & Time Builder) product allows you to simply
place the hard obstructions and leave the placement channels (as small
as 5% for the placement channel) and the product will take care of the
gate level placement.
In designs I have run into with designs with DSP cores, bit slice
designs next to large cache RAMS, and big Mixed signal blocks with hard
obstruction data converters and the current solution is to hand place
and then do the holding area trick. The other vendor solutions I have
tried in the past have not been able to get clean solutions with
anything over 40% hard obstructions -- even though the vendors claim
higher. So far the InTime stuff has not fallen out as yet in the 70%+
fixed position situations.
Second, InTime can support core I/O and core power. Core I/O is just
ramping up - but most of my BGA clients are using core power. These
require fairly complicated peripheral to core fan out solutions to wire
up. Their Time Architect product fully supports the core power
placement and can floorplan these redistribution layer so it does not
have to be done manually. Currently, the BGA interface is done in full
custom polygon layout for most of my clients. The other players -
Magma/Synopsys/SPC are just getting to the issue of core I/O & power
and are a bit late at getting a solution out there. This feature alone
is a 2-3 week project reduction and is less prone to errors. If you
are building a 700+ pin device, and are going the way of vertical probe
cards - the floorplanning level fixing of the core I/O & power means
the difference of 4-6 weeks after the part is done to order and get a
probe card to be in time with the device, and having the info early
enough to have a probe card back when the wafers are ready.
Third, InTime's STA tool. Most of the other STA tools on the market
have to be correlated back to PrimeTime which is the default signoff
tool. It is very difficult for most tools to have a high degree of
correlation as the correlation factor can shift based on the size
of the block. InTime got around this problem. They use the same
setup, budgeting and constraint files as PrimeTime so you do not need
to build a correlation file and qualify their STA tool. They are also
conceeding the fact that most customers will still want to sanity check
their design with at least one PrimeTime run. To make this easier,
the InTime GUI has a select box for EITHER the InTime STA tool or
PrimeTime. All the scripts and runtime environment are unchanged
except for the engine. This allows the customer to plan for reuse and
bless off each block as a final PrimeTime run after working with their
faster STA tool, rather than waiting for the whole chip to be done.
They actually have a fairly robust STA tool handling false path, thru
pins, time borrowing, etc. Most of the fabless clients I deal with do
not have the manpower available to do the correlation with PrimeTime
to use another tool -- this way you can have a floorplanner and placer
and trust the results will work in the design.
Forth, the last cool thing about the InTime products vs the tools from
SPC/Synopsys-Avanti/Magma is their pin handling on hierarchy. The
other tools do not do a very good job of multiple pin layers (over 2)
on a peripheral edge of a module or block. For high density blocks
that may have 4 or more interconnect layers for the pins, the other
planning and gate placers put a lot more blank routing space for their
estimates than InTime. The InTime solution was closer the optimal
route configuration. People doing high density CAMS and other
specialty memories interfaces have had lots of problems getting these
interfaces to be compact - the standard answer seems to be blow it out
wide and stuff buffers in it until it can be balanced. The typical
output from one of my company's video data converters is a 3 level pin
interface and it has ended up being a hand place and partitioned cell.
The folks at InTime are claiming a bunch of other cool stuff in their
tools - maybe so - I have not run into those other things with as
bothersome workarounds required as these 4 points. Since my speciality
is Flow development and optimization, killing the workaround steps at
my clients is the biggest deal, and InTime certainly addresses the bad
one for the 90 nm and 65 nm nodes."
- Pallab Chatterjee of SiliconMap
"I did go see the InTime demo booth at DAC and their tool looked very
interesting, however, my management can't seem to make up their minds
weather we're looking to upgrade infrastructure or not so I've pretty
much dropped the whole thing for lack of interest. InTime looked like
a pretty neat idea - getting RTL jocks an idea of what their code will
look like synthesized and playing around with various floorplan ideas
while still in RTL development. But InTime comes with the caveat of
all other such tools: it would be a considerable methodology shift to
really use their tool. Until they've proven that they'll be around
for a while I wouldn't recommend InTime because if you spend all the
time and energy to work the concept into your methodology and then they
go out of business you'd really be in trouble. It looked a little more
involved than just adding a point tool to the flow so if it went away
after you've adopted them it would be very bad."
- Brian Kuebert of Hitachi
"We have been working closely with InTime with an AE on site for the
last couple of months, and prior to that on concepts. Their tool
suite takes you from an RTL to a placed gate level database. We
just got our first block through and the InTime area estimation
between RTL functions and actual gate level synthesized with
Synopsys was within 4%. It's a small test case, and we would have to
do more before we can really see how close it is. 1/2 of the block
was memory also.
We have not evaluated InTime's timing accuracy yet. But the concepts
of placing RTL functions, and getting the right setloads and proper
wireloads are a much better approach to driving DC.
InTime's floorplanner a fairly complete, with advanced features such
as easily pushing down power grids from the Flip Chip top level into
the blocks, and more importantly, a good optimization engine for pins
on soft blocks.
The key differences relative to what InTime offered at DAC last year
is that their floorplanner is now usable, and their area and timing
estimators are now released. (We were an early beta site.)
Our goal is to get the InTime estimators qualified over the next 2-3
months and to roll it into production on the next generation of
network processors."
- George Serhan of AMCC
"I am currently evaluating InTime's Time Planner, now. I have no hard
data yet, so most of info comes from their DAC suite demo.
The most impressive thing it has is it can deal with RTL code. As far
as I know, other floorplanners begin with a gate-level netlist as a
starting point. That makes your first gate-level netlist as a seed to
random number generation. Depending on the initial guess, your
floorplan result can be quite different. On the other hand, beginning
with RTL, the InTime product can have more degrees of freedom.
Another aspect of InTime product is that it can provide visualization,
a bridge from abstract to layout concept. However, the InTime product
does not provide (I think) user controllability well. After binding
RTL codes logically, I could not find any command or window form to
specify constraints to each logical blocks in detail. I can put
constraints only for the whole chip. And I saw minor run-time errors.
A slow runtime can be another disadvantage. As far as I know, InTime
product is built with Java. It can be an advantage when InTime product
is used over the network. But in case of floorplanner, most users use
it as a stand-alone tools. Incentia developed their first version of
DesignCraft using Java, but they found that it is very slow, so they
re-built their DesignCraft using Qt or Gtk libraries. InTime's slow
reponse in drawing windows and manipulating GUI can make users feel
that the tool itself consumes too much runtime. I think the InTime
developers have to consider this point.
Time Planner & Time Builder, are a good concept in dealing with RTL
as a starting point, but they are somewhat immature. There is no 100%
perfect software with no errors. But I expect a useful tool should be
at least 95% perfect. InTime products seems to be still 90%: still
some minor tiny errors, but sometimes these made me stop proceeding to
the next steps, while I was evaluating it.
But if they make up for these 5% in near future, it will be a good
alternative to SPC, or Floorplan Compiler -- both of which are too
expensive and massive in my opinion."
- TaeHoon Kim of Hynix Semiconductor
"First Encounter demo - This was supposed to be FE-ultra demo in a
suite (I learnt later) & all I got to see was their poor tired AE
ramble thro FE's powerful capabilities. I don't blame the AE for
the poor show, after all it was the last day for demo suites.
Tera's TeraForm - saw a poor floor demo, the guy got into a rat hole,
I had to get out of that demo!!"
- [ An Anon Engineer ]
"4.4.2 Tera Systems - Teraform
This tool is from a smaller EDA company sports several interesting
features wrapped up in one package. From their datasheet:
- Synthesizable-RTL input supports industry standards.
- Processes multi-million-gate SOC designs at interactive speeds.
- Accurate RTL area and timing estimation enables early-stage
what-if analyses.
- Automatic full-chip hierarchical design partitioning improves
chip area and speed.
- Automatic hierarchical design budgeting for improved chip
performance.
- Automatic timing-driven floorplanning creates an RTL silicon
virtual prototype.
- Powerful design visualization capabilities enable RTL
micro-architecture optimization.
- Outputs accurate placement-based wiring parasitics and floorplan
constraints to accelerate gate-level timing convergence.
- Unified hierarchical design database with procedural language
interface improves designer productivity.
They attempt to address some of the same problems that PhysOpt
addresses. It seems that TeraForm could be a very good first pass
check on RTL, likely to be more accurate than statistical wire load
models. They also have a library of 'TeraGates'. The closest
approximation to this library is a DesignWare library pumped up on
steroids with physical design data sprinkled in.
Like most physical prototyping tools, the fifty-dollar question is
'How close is the correlation between the estimates and the real placed
design?' It would be interesting to find out.
The interface looks very slick also, and might be very valuable as a
learning tool for inexperienced RTL designers. It is very easy to view
a gate level representation of the RTL and examine the logic inferred."
- Eric Decker of Paradigm Works, Inc.
"5.2.4 Tera Systems
Tera Systems offer two products: TeraForm-VP for Virtual Prototyping
and TeraForm-RDC (RTL Design Consultant) for "physical" analysis of
the design at RTL. Basically these tools shall enable RTL-Handoff
to the backend flow. Both have full chip capacity - not only blocks.
This is achieved by another level of abstraction what they call
"TeraGates". It basically treats e.g. an adder or a multiplier as one
block rather than a sea of gates.
TeraForm-RDC has a large set of user configurable rules that are
checked on the RTL to quickly identify potential problems later in
the physical flow.
TeraForm-VP reads in synthesizable RTL code and does an automatic
partitioning of the design to quickly identify critical issues.
It supports several industry standard timing and placement formats
(like LEF/DEF) and has advanced cross-probing facilities when doing
the timing checks."
- Raimund Soenning of Philips
"Tera Systems sells a tool that goes from RTL to a block level floorplan
and timing constraints. It has some unique hooks for RTL debug. It
synthesizes your code and displays your critical path in terms of RTL
level blocks (adders, multiplexers, etc.). If you click on a block in
the critical path diagram, their TeraForm tool will highlight the line
in your code that synthesized to that hardware. This means that this
is a useful front end for RTL tradeoffs even if you have another design
planning tool. They say they are working closely with the First
Encounter people (recently bought by Cadence) even though these two
tools are theoretically lumped together as competitors. TeraForm can
output only a block level placement, with no notion of legal cell
placements, power buses, etc. First Encounter (or Synopsys Floorplan
Compiler) can produce a "legalized" placement that a physical synthesis
tool really needs for best operation. They said sometimes someone
tries to do a head-to-head comparison of the two tools and winds up
buying both. Before being usable for a new library, Tera takes the
cells of the library and goes through a time-consuming process of
synthesizing and routing various standard RTL blocks with various
constraints. For example, they would create 4, 8, 16, 32 and 64 bit
adders, and would do the smallest possible implementation, the fastest,
and one in the middle (plus some other corners, apparently). This
provides hard speed and area numbers for the basic RTL components you
will be using, without the need to do any synthesis or place and route
within the Tera tool. This library of "Teracells" is provided by your
vendor just like a Synopsys library. Tera charges you if you want the
characterization tool for your own library. Your RTL is then
synthesized into these Teracells, and they are the units that are
placed in the floorplanner. Bill Shipley, my Synopsys guru, noted that
the characterization process apparently uses only basic DesignWare, so
the fastest multipliers and adders wouldn't be in the library (this
might create spurious reports of timing problems). They claim their
RTL level timing analyzer is typically within 10% of Primetime, which
most customers are happy with. As mentioned, TeraForm does block level
floorplanning, based on the areas of the Teracells, and does time
budgeting of the blocks. It also does some linting functions, which I
believe are there because they want to be the gatekeeper for ASIC
foundries and they know they'll need at least basic linting to do that.
It also checks for things like missing constraints. Tera emphasized
they are used by IBM, LSI and NEC.
InTime Software sells three Verilog-only tools that go from pre-RTL to
gate level planning. Their pre-RTL tool is for design feasibility and
first creates a library of big building blocks (adders, multipliers,
etc.) using your library and synthesis tool. Their salesman said that
this tool competes mainly with in-house spreadsheet based systems.
Their RTL level system is like Tera or Blast Prototype. Their gate
level tool is a floorplanner than can be tuned to either Synopsys or
Cadence (interesting!). The InTime salesman and the Tera salesman both
said they had never competed in an eval - don't know what this means.
Icinergy sells a tool for architectural tradeoffs at the pre-RTL level.
It produces LEF, DEF, PDEF, a Verilog netlist and SDC constraints. I
didn't get a chance to see it.
Monterey Design bought Aristo and got their IC Wizard tool that does
automatic block placement."
- John Weiland of Intrinsix
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