( DAC 02 Item 12 ) ---------------------------------------------- [ 9/10/02 ]
Subject: Quickturn, Mentor, Axis, IKOS, Tharas, Bridges2Silicon, SimPOD
LAWYERS, GUNS, & MONEY: The hardware emulator/accelerator part of the EDA
industry acts like one big soap opera. For years Mentor & Cadence Quickturn
have been suing each other in court for patent infringement. This year IKOS
was acquired by Synopsys. Then it wasn't. Then IKOS sued Axis for stealing
their patent. Then IKOS sort of was aquired again by Synopsys, until Mentor
put in a higher bid. Mentor finally acquired IKOS. Then Axis *sued* IKOS
for patent infringement & IKOS decided to sue Cadence Quickturn, too! The
only one *not* caught up in a lawsuit is Tharas. (There used to be another
very small player in this niche called "SimPOD", but they weren't at DAC
this year. I'm not sure if they still in business or not.) And the newbie
Bridges2Silicon hasn't been around long enough yet to get sued.
"It started with the Quickturn/Pie lawsuit and has become an industry
tradition. I can't imagine a major player not being sued. As far as
I know, the legal profession has made more money off of emulation than
the emulation vendors have."
- Gary Smith of Dataquest
"4.4.1 AXIS Systems Xtreme II
Key features and advantages of AXIS' Xtreme:
- Seamlessly integrates emulation, acceleration and simulation into a
single verification environment
- FPGA based (Xilinx)
- Interconnect technology is 'event-driven'; data transfer only
when it is necessary
- Hot swapping capability from emulation to simulation and vice versa
- Profiler by SW simulation
- Recorder for 'VCD on demand'. Everything signal is available at all
times after just one run. The data is stored in very small files
(surprisingly small - but the HW is actually used to regenerate
the traces)
- In-circuit verification - meaning it is e.g. possible to connect the
outside world to the simulator on the workstation
- tb_call command enables load and dump of data on the fly (or Verilog
command $DISPLAY)
- Takes up to 50M ASIC gates (in a box not larger than a bigger
workstation)
- 30x to 35x faster as RTL (nVidia benchmark)
- mixed-language capable
- one database for simulation, acceleration and emulation !!!!
- Debussy integration with active annotation on RT level.
- PCI speedbridge available
- Requires processor farm for compile
4.4.2 Mentor VStation 15/30M (formerly known as IKOS VStation)
Mentor just recently acquired IKOS Systems. Hence Mentor at the moment
offers two platforms for emulation/simulation accelerators: Celaro and
VStation. They have a roadmap two merge (the best of) both
technologies until 2004. Up to then both will be supported in parallel.
The presentation I attended was about VStation:
VStation is available in different sizes (dependent on boards in the
frame): 5M, 15M and the latest addition 30M. An interesting derivative
is Replicate which is basically the same hardware but with only little
debug capability for a much less expensive prize (4 cents/gate). These
systems are intended for SW developers - possible scenario: one
complete VStation + several Replicates give HW and SW designer more
productivity as they share the same database for the boxes but can work
in parallel.
Some key numbers + features:
- Speed 1 Mcps in emulation mode, 300-400 kcps for Cosim
- Compile time 5 Mgates/hour - to be done on a PC farm in rack which
comes together with the box in a bundle
- Download lasts couple of minutes
- FPGA based (Xilinx)
- Interconnect with (patented) VirtualWire technology (time division
multiplex bus between FPGAs)
- Integrated Debussy front end (for VHDL soon)
- Debug trigger & windows need to be set upfront but no re-compile
necessary if they need to be changed
- Requires SUN workstation as host (will be given for free with the
box - probably)
- Interconnect to the box with SCSI cable - for Co-Modeling an
additional PCI card is used in the host workstation
VStation can be operated in different scenarios:
1. In-circuit emulation
2. Co-Modeling with high speed test interface - they claim to be
1000x faster than pure SW simulation
3. HDL link - here the user uses the simulator window he is used
to and the box just speeds up the simulation time (performance
increase up to 20k) for about 10 kcps. At the moment there are
still 2 windows which will be merged with the Debussy integration
(as already said VHDL support end of the year).
A deeper look on the Co-Modeling mode:
The testbench running on the host work station is written in C (or
SystemC). There is a webpage available showing good practice and some
examples. The interface to the VStation has a standardized API. They
call it MCT (Multi Channel Transport). The communication to the box is
transaction based with the BFMs (Bus Functional Models) on the
VStation. They need to be written in RTL code. But there is also
already a library for standard interfaces available. It is possible to
create reactive testbenches (e.g. load and dump of memories triggered
by certain events).
The demo Mentor was showing used a self-written command line interface
on the host workstation. For data recording a trigger file needs to be
created very similar to how you would setup a complex trigger condition
on a logic analyzer. All signals are traced and shown in one window.
Side note: there are rumours that Mentor laid off all the former IKOS
people in Germany. Hence support here seems a little bit questionable."
- Raimund Soenning of Philips
"8.0 Hardware Accelerators, Emulators and Prototyping Systems
IKOS (part of Mentor) now emphasizes emulators more than accelerators.
Their new boxes use Virtex 2000 parts and can simulate up to 30M ASIC
gates. They sell a version for hardware debug and then a cheaper
replicant version for software development.
Axis sells a box that sounds like a cross between an accelerator and
an emulator. It maps your design to processor elements on FPGAs. They
say they can simulate up to 50M gates in a relatively small, cheap box.
They say then can switch between acceleration and their own software
simulator on a clock by clock basis ("hot swapping") and can do "VCD
on demand".
Quickturn (now part of Cadence) was the original big emulator company.
They say their biggest box when fully populated can simulate 128M gates
& 64GB of RAM. I don't know if a "gate" is the same thing for them and
their competitors, but their boxes sure are BIG. They are designed for
up to 16 simultaneous users, and are aimed at RTL as well as gate level
debug. Quickturn is partnered with TransEDA & Verisity, and interfaces
well with Verisity and NC-Sim. They said dropping a new probe (always
an issue with emulators) takes no time at all.
Tharas sells what may be the last true hardware accelerator. As one
would expect, it can compile faster than an emulator (simulation is
probably slower). They can put up to 32 million gates and 1 Gig of
memory on one of their boxes. It is Verilog only and can work with
NC or VCS.
Aptix is one of a number of companies that sell FPGA based boards for
prototyping your system. This type of verification is the most time
consuming to set up and the fastest to run - you use this to verify a
design for millions or billions of clocks. Their new boards use Virtex
6000 parts and have all I/O available (not easy). They say you can
chop your ASIC into their FPGAs using the Synplicity Certify tool
(interestingly, Synplicity did not mention them at a recent demo I
saw) but they also have their own Design Pilot tool. They now rent
systems for 6 or 12 months if you don't want to buy one. The also have
a new cheaper system for software development that doesn't have the
hooks for hardware debug; your hardware guys get a more expensive
version and the software guys just use the cheaper one. One note from
last year: apparently this type of system has low utilization of FPGA
gates for modeling your system, so when a vendor quotes you gates, you
have to be sure if they mean FPGA gates or gates in your ASIC, which
might be 5X different or more. I was fooled by one of Aptix's
competitors last year when trying to compare them.
Bridges2Silicon sells a tool to add probe points to your prototype.
You give it your RTL and a list of things you want to observe. It
spits out new RTL with their debug logic added, which you then
synthesize to build your prototypes. They also have a way of adding
this to cores without giving away all the RTL in the core.
Verisity now sells a testbench accelerator tool that allows you to
synthesize your "e" testbenches and run them on accelerators/emulators
from IKOS, Mentor and Quickturn. I attended a demo where they
emphasized that they facilitate functional coverage analysis much
better than Vera.
Emulation and Verification Engineering sells a PCI card with a lot of
Xilinx FPGAs and 2 Gig of RAM for simulation. They say they can
simulate with VHDL, Verilog, C or C++ (don't know how it ties to
simulators). They say they use read-back from the FPGAs rather than
recompiling for a probe, which saves a lot of time in debug.
Experience First, Inc. sells some patented technology, apparently
called Raptor, to build your own emulator, plus you get a demo board
suitable for a small design. They say every customer they spoke with
wanted a different size board, so they thought this was the best
product for pleasing everyone.
Dynalith sells a small box with an FPGA and a processor. You hook this
into your system for in-system verification of your design before you
have a real part. The FPGA does the interface to the system, and the
processor runs a C language model of your design.
Agilent sells some way of hooking real parts into a simulator; didn't
get the details."
- John Weiland of Intrinsix
"I hear that Quickturn dumped Mercury (old FPGA/ASIC based emulators)
and are going with the CoBalt/Radium solution that they are now buying
from IBM, engineers and all. I worked with IBM and the gang on the
early Radium box. It seems that Radium is not scaled right to do the
job (for sale at least, IBM has large ones in-house that work well for
them). The CoBalt line (at its core) is really a processor based
simulation construct (if I recall right). They are based on the old
Eve/Evette line of mainframes at IBM. They are cycle-based, which I
think is a big disadvantage when dealing with resolving non-
deterministic races in design code. One HUGE disadvantage of Quickturn
stuff is that they do not handle gated clocks. I am not sure if CoBalt
can deal with them, but the Mercury system (and previous System
Realizer) was hell in dealing with gated clocks.
The big problem with Quickturn was the HW interface to the design. And
getting rid of design constructs that they could not deal with, and
reducing scan and other non-essential items to get large designs to fit
into the HW array. And then after that, compiling the beast into the
box, and then (pant pant) making sure that the emulator system was up
and running (diags are hell to run). Reliability with their systems
was pretty low. Also once you get the thing running, it is pretty
slow. A big problem with CoBalt was that the more you stuff the box,
the slower it goes. I have seen it run at 500 KHz max. Their cost is
high, it sucks power like you cannot believe, and and they like to sell
you an army of people to run the systems & that costs big bucks. I do
not see a bright future for them at the prices they want from Cadence,
and with IBM selling them all their lot. I think that Radium could
sell, if they had a clue what it was about. They tried to rope me into
that arena. I declined.
Moving on to Tharas (a small upstart that seems to be teetering on
going under) they have a HW accelerator, but no SW simulator. Thus
they have to rely on VCS or NC-Verilog to run, and they have to use
the links to PLI through NC-Verilog and VCS. Seems akward. They also
have their own ASIC, and thus are stuck with re-design to improve
speed and scale and performance. Tharas cannot deal with certain
design constructs like latches, and they are also a cycle-based
simulator.
As for Axis, their system is a lot simpiler to use than Quickturn
emulation, they handle gated clocks, and they deal with latched based
designs. They are also event based, and they have their own SW
simulator. The Axis SW simultor is slower than VCS ot NC-Verilog,
but once you are in the HW free-run mode, it runs upward of... oops,
I cannot disclose that. But it is fast. Their support model is OK.
They do not support PLI 2.0/VPI yet. But VCS is still dealing with
that as well. And PLI is not acceleratable anyway. Axis does have
scale though. Their new Xtreme-II system is Xilinx based, and can
handle large microprocessor designs. Axis also can run self-checking
diags in a matter of minutes, and their mean time to failure is
amazing. Their boxes simply do not fail. They also require no
special power, space, or labs. Axis boxes run on 110v and take up
about as much room as a Sun Ultra60 or SunBlade1000. Their HW is very
easy to install and manage. Their SW simulator runs pretty much the
same as VCS or NCV. Slower, but they do not push the SW side as being
the speedy simulator. I think they are scaled right, positioned right,
and have the right tools. Lots of big companies are buying their stuff
(Cisco, Sun, Sony, Phillips, Intel).
Meta... every time I ask Mentor about Meta, they say they cannot say
anything due to gag orders from legal suits with Quickturn. Not
available in the US and Germany."
- [ An Anon Engineer ]
"Emulators/accelerator: Axis is the most easiest to use and Axis offers
both acceleration and emulation. Axis has good technical support as
well. Quickturn is behind in software and not user friendly for debug.
The Quickturn hardware is focus on emulation and not much improvement
over the years. IKOS offer acceleration but not as mature as Axis."
- William Lam of Tvia
"I used Quickturn once, helping another engineer debug a test that she
was running on a chip I had designed. It seemed a bit cumbersome in
that only some of the signals were trace-able. The model had to be
recompiled at least 3 times before the signals we really needed to
see were visible in the waveform viewer. The machines are very
expensive, but certainly speed up regression testing. The viewer
itself was vastly inferior to the one included in Mentor's Modelsim."
- [ An Anon Engineer ]
"Emulators: Tharas has good solutions and may yet come out ahead."
- Jai Durgam of SiImage
"We are using the IKOS harware accelerator box with ~ 5-10 times speed
improvements. We use Verisity Specman for building our testbenches.
In some aspects, such as directed random testing, we find it quite
useful. However, we have noticed degradation is testbench speed in
some cases which is making our hardware accelerator less effective."
- Mehran Bagheri of Multilink Technology
"We are using IKOS accelerator. The interface is a mess. A lot of
improvements possible there. We are exploring to use Novas debussy
tool has a new debugger interface."
- Pascal Gouedo of STMicroelectronics
"We use IKOS and it's very important to us. Emulation is still at a
point where it's very, very expensive (to buy and to use) so it's
great if you can do it, but not everyone can."
- [ An Anon Engineer ]
"We put some QuickTurn emulators to work here, and they have helped
find some bugs. Took a fair amount of work to set up the hardware
interface between the emulator and the rest of the system it talks
to, but finding the bugs paid for that work.
We also have several IKOS boxes (some big, some small) we haven't
used in years."
- Mark Wroblewski of Cirrus Logic
"I know the founders of Bridges2Silicon as I worked with them at
Exemplar and (Doug Perry) back at Daisy. What I can tell you outside
of non-disclosure is that it is a good tool at the low level to
back-trace designs into simulators. It is very much like the low
level emulator developed at Quickturn when I was there. (Bob Hasselen
was working on it, I forget the name as it was a complete marketing
flop because that tool required a probing mechanism like a digital
analyzer to look at the results and get it to work). Bridges2Silicon's
novel approach is to feed the design & test stuff from HW back into
the simulator trace files and look at results in a waveform viewer."
- [ An Anon Engineer ]
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