( DAC 02 Item 11 ) ---------------------------------------------- [ 9/10/02 ]
Subject: TetraMAX, Mentor FastScan & testKompress, LogicVision, Genesys
SAME OLD, SAME OLD: Not much has changed in the past year in the test part
of the EDA market. Synopsys TetraMAX appears to dominate the mindshare of
ATPG users with Mentor's FastScan struggling to change that impression.
LogicVision pretty much owns BIST, again with Mentor working to take over
that market but not quite there yet. Mentor does have great scan insertion
technology, though. Oddly, only one person noticed Mentor's brand new
testKompress tool this year. And Genesys' BIST-DR (which does post fab mem
repair) got noticed by a few users again this year, too. With all these
mentions in test overall, I'd keep my eye on Mentor in this niche, though.
"It really was moving against the stream to convince my management to
bring Genesys in house. Shortly after I started here, I recognized
that we lose about 30 to 50 % of our yield due to memory failures.
It was almost accepted that it is the way it is.
I took a stand to prove that wrong. After I learned that Genesys had
a soft memory repair, I tried to bring them in and make arrangements
with all the design managers to hear what Genesys had to offer. With
all the busy schedules & deadlines, change is not a soft spoken word to
many, but I got enough acceptance to cut a license purchase. Since
then, we used Genesys on two projects. We used their tool as simple
memory BIST (without repair) and it worked well. But that was not my
main attraction to Genesys. Two weeks ago, our first chip came in
which used their memory soft repair. To everyone's surprise, it
salvaged quite a bit of yield! So much so, that I'm not allowed to
give out the actual numbers. Let's just say people here are happy now
that we brought in Genesys memory BIST repair."
- Max Hamidi of Centillium
"Genesys is the only tool I have used which runs memory BIST and does
repair. We did explore Virage, but it was prohibitively expensive.
It took me some time to get a handle on the Genesys tool. It's not a
difficult tool to use, but we did not get any formal training. What
really helped during this phase was the support. Bejoy came personally
and helped out with problems. The Genesys tool had an issue with Ambit
synthesis. We worked with Genesys so the tool could generate good
Ambit scripts. Towards tapeout of our chip in April 2002, the tool had
issues with generating tester compatible vectors. Again, we got good
support from Genesys.
Post silicon experiences: We did get a slight improvement in the yield
due to data repair. The traffic management chip we taped-out has about
9.6M of memory. We used their BIST-DR on all memories >128K. So far,
there has been a 2-3% improvement in yield due to repairable memories."
- Sanjay Wattal of Azanda, Inc.
"Now we are using Synopsys TetraMAX and Mentor Fastscan. Both of them
are good tools. We continue to use both. The difference between the
two companies is BIST support. We use Mentor tools not only FastScan
but also MBIST Architect and LBIST Architect. BIST technology is
important for especially big design."
- Zenji Oka of Ricoh
"The new Synopsys hierarchical DFT tool is buggy & caused some headaches
for us. Synopsys helped us get through the problems. No issues with
TetraMax. LogicVision BIST tool is also buggy and the support is not
good."
- Mehran Bagheri of Multilink Technology
"I had a contractor do TetraMAX for me at my last job. TetraMAX seemed
much better than the old Synopsys Test Compiler, but it still seems to
hang in certain situations (don't remember what)."
- [ An Anon Engineer ]
"Test tools: So far I only know Mentor offered more complete solution."
- William Lam of Tvia
"I think the biggest lie around is that Synopsys' scan insertion flow is
any good. It's terrible -- does things behind your back and produces
wacky results that you end up cleaning up by hand. Ick."
- [ An Anon Engineer ]
"In the past we have been faithful to Mentor as far as DFT goes.
However, things are slowly changing. I've started using Synopsys DC
and PhysOpt for DFT insertion. We still use Mentor for ATPG, but
may move to TetraMAX later on."
- Himanshu Bhatnagar of Conexant
"We have a very good DFT team that has used TetraMAX and Logicvision's
BIST. They are familiar with Mentor's tools & would be very reluctant
to move away from TetraMAX and LogicVision. We used Virage, but with
more problems that we would care to see and pretty bad support on the
problems we do have. Virage is miles behind Synopsys or LogicVision
on support.
We use both Verplex and Formality. Verplex is still better in many
areas but Formality has made impressive improvements over the past
18 months. Synopsys gives better support and is easier to deal with
than Verplex."
- [ An Anon Engineer ]
"We are using Synopsys TetraMAX. In the past, we were using Mentor's
tools. TetraMAX is easier to use and has a better interface to
debug problems."
- Pascal Gouedo of STMicroelectronics
"Our company has had some limited experience with TetraMAX. We had no
complaints. It did what we needed it to do."
- John Filion of Theseus
"TetraMAX is mainstream tool for DFT/ATPG. LogicVision is mainstream
tool for BIST. Verplex is still the best Formal Equivalence Checker."
- [ An Anon Engineer ]
"We use TetraMAX now. Taped out a design early this month using it.
Worked well. Don't use equivalency checkers here. Used Formality
a couple years back at another place, liked it pretty much then."
- Mark Wroblewski of Cirrus Logic
"We recently took a long look at the various DFT tool suites available
to decide where we want to go with our DFT flow. It involved looking
at Synopsys, Mentor Graphics, and LogicVision:
ATPG
TetraMAX & Fastscan are really the only contenders amongst the three
for a decent ATPG. LogicVision does have an ATPG, and it has been
improved significantly recently, but it still produces pattern sets
50%+ larger than the other two. The Synopsys and Mentor tools are very
similar, but we found that Mentor was a bit clunkier. TetraMAX is much
easier to debug, especially if you are running ATPG on a design that
didn't get it's DFT inserted by Synopsys. The use of STIL as an input
format for the test setup is much better than Fastscan's test procedure
files. Overall we found test pattern generation results between
Synopsys and Mentor to be very close.
As for Mentor's testKompress, as I understand it this is just LFSR
reseeding of something that looks a lot like a logic BIST. Not exactly
a new idea, but still a good one, and not necessarily an easy one
to do right.
DFT Insertion
All three tool vendors have a decent effort in for this component.
What I mean by DFT insertion is scan insertion, test point insertion,
and in some cases DFT retiming. LogicVision probably leads the pack
with a decent test point insertion tool, and their capture by domain
methodology, which prevents hold violations across clock domains, and
allows you to use a single clock for your scan (this can save a lot of
patterns down the road). Mentor tools are pretty good at this, and
Synopsys, although very reliable, are probably at the bottom because
they require dc_shell (and inherit all of the limitations that go
along with it.)
BIST
The best membist tool out there is still LogicVision's. Mentor is
catching up, and Synopsys is just starting out, but they include it
in DesignWare, which could make them a cheap alternative if you already
have DesignWare licenses. LogicVision's integration and flow are years
ahead of everyone else, and their single bit test data makes routing
easier. LogicVision is also the only company whose logicBIST I would
put in a design, Synopsys doesn't have one yet, and Mentor's is still
lagging behind.
Verification
All three can generate suitable Verilog testbenches. We have had
problems with the parallel loading testbenches from all three at one
point or another, but got them to work eventually. Synopsys has the
most elegant looking ones, but as long as they run we don't really
care. All three made working serial loading testbenches. As for STA
scripts, only LogicVision generates them, and they don't work without
a fair bit of modification anyway.
Hierarchical DFT
Hierarchical DFT is basically the idea of chopping up a design into
distinct chunks, and generating the DFT for each seperately. So if you
had a 4 million gate design, you could test it as ten 400,000 gate
designs instead of one big 4 million gate design. LogicVision is the
only company with a production release of a product like this, and it
does work, although I can't say much more than that. Synopsys is
aggressively pursuing this niche, and Mentor has heard of it. We will
be watching this aspect of DFT closely.
Overall, I would say that the best flow out there today is a mixed one
with LogicVision for everything except scan ATPG. Although I prefer
TetraMAX for the ATPG component, Fastscan is basically just as good."
- [ An Anon Engineer ]
"LogicVision is good, works well, easy to use and no reason to switch.
TetraMAX, same thing. Virage is too pricy."
- Jai Durgam of SiImage
"LogicVision BIST apparently is the leader in DFT solution with the
capability to tie to test program for analysis."
- Wenhua Zhao of Fujitsu
"Logicvision sells tools for Built-In-Self-Test (BIST) for both memories
and logic. They will emphasize that technically they are selling IP
(the BIST circuitry they use), which I assume means the software itself
isn't that complicated and is easily duplicated. For memories, BIST is
easy because the structures are so regular. The problem with logic BIST
is that you can't just do it from the registers. For example, if
there's a zero detect on a 32-bit adder output, random patterns would
result in this signal being active only once every 2**32 clocks. Any
logic downstream from it would never be fully tested. Logicvision has
software that identifies where to add extra test points (like a zero
flag) so as to get high coverage with fewer clocks. New this year is a
desktop debugger that will allow one to isolate memory faults to a
single bit, and can isolate logic faults using an on-the-fly fault
dictionary similar to what Synopsys Tetramax does.
Syntest sells a complete line of test tools and is teamed with Cadence
(I wouldn't be surprised of Cadence buys them). In addition to their
memory BIST product, they now have a logic BIST tool. They say
their ATPG vectors are more compact than Synopsys or even Mentor. They
also have a very interesting multi-capture scheme but I lost the darn
brochure on it.
Genesys makes BIST for logic and memories (including CAMs). Their
memory BIST allows for soft repair of faults (note that the new
Virage memory compilers allow for both soft and hard repair). They
also have a boundary scan insertion tool, which they say has been
more automated for this year.
Circuit Semantics sells a tool that helps Mentor's Fastscan understand
full custom blocks.
Fluence owns Opmaxx, which sells mixed signal BIST for measuring PLL
jitter as well as for testing ADCs, DACs, amps and filters. Fluence
also sells that translators that go from a standard format like WGL or
STIL to the tester specific format and helps the test engineer tweak
the vector on the tester.
Intusoft sells software for automatic test generation for analog and
mixed signal parts. I'm not even sure exactly what that means, but
their literature looks very good.
Astek sells a JTAG insertion tool that they say is much cheaper than
their competitors and easier to use.
Asset InterTech and their competitor Intellitech both do software and
hardware to test boards via boundary scan. You give the tool the
netlist for the board and a description of the boundary scan on each
of the parts, and it will generate tests that check all the
chip-to-chip interconnect on the board. They also sell the testers.
Intellitech now sells a scheme for system level BIST using boundary
scan. Vectors are stored in a flash chip and there is a separate
controller chip (one per system). Their scheme will test the
interconnect on and between your boards."
- John Weiland of Intrinsix
"TetraMAX is good, we gen ATPG vectors for our last chip with that,
no problems. LogicVision BIST was used for RAM BIST & those vectors
also ran thro' without any issues. One thing we want to try is
LogicVision's logic-BIST. I saw the Formality booth demo, impressive
but also heard from outside they in the past have come up with "false
positives", dangerous!!"
- [ An Anon Engineer ]
"I worked with LogicVision quite a bit, specifically with one of their
FAEs who was assigned to our company. They gave us all the tools we
needed to create BIST HDL code on our own, but we didn't have time to
learn them so we continued to rely on the LogicVision FAE to generate
the code for us. (The code is basically a wrap around memory modules.)
This slowed down development somewhat, produced more customer <-> LV
code iterations than would have been otherwise req'd, and led to some
rush releases of BIST code by the LogicVision FAE because he was simply
assigned too much work... this led to a few bugs, but no show stoppers.
The main criticism I have of LogicVision is that their automated VHDL
code generators produce hard-to-read, idiosyncratic and inflexible code
which the customer is nevertheless ultimaetly responsible for and must,
on occasion, modify (e.g. to fix bugs). Also, some VHDL constructs are
not supported. As a result, their generated code (specifically their
testbenches) is not easily adaptable to different test environments,
and tedious testbench hacking had to be done in some cases (for example
conversion to FTPG clock periods in the presence of several clocks
whose periods are consrained by the FTPG tester). The FAE was much
stronger in Verilog than in VHDL, which was a handicap for us also.
Overall, the relationship was satisfactory (the ASIC BIST works fine),
but there is certainly room to improve efficiency at LogicVision."
- [ An Anon Engineer ]
"TetraMAX, yup. No problems.
LogicVision BIST, yup. Relatively OK. Some annoyances in STA since
it creates some ugly multi-cycle path and what not in the controllers
and we generally try to be MCP/FP-clean in our design to simplify STA
and back-end constraints.
We're dumping Synopsys scan solutions to use Mentor DFT Advisor for
scan insertion (but keeping TetraMAX, that works well). Mentor does
fewer brain-dead things, and is probably the best point-tool scan
insertion out there. It also has higher capacity than DC-based
solutions. Plus it costs less. Talk about an all-around win.
Verplex, yup. 64-bit version did a nasty 6M+ gate hier-to-flat
comparison that we didn't think could be done. Block-level
RTL-to-gate is plenty fast for us, runs on Linux, yippee."
- [ An Anon Engineer ]
"Take a look at IBM's test tools! They're *really* powerful, and free
with the NRE. We've saved weeks/months of labor using them, compared
to Synopsys/Mentor test tools."
- [ An Anon Engineer ]
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