( DAC 02 Item 10 ) ---------------------------------------------- [ 9/10/02 ]
Subject: SynaptiCAD, Forte Perspective, Esterel, TNI-Valiosys
OOPS, I FORGOT: You've got to also add SynaptiCAD, Forte Perspective, and
TNI-Valiosys to that list of Old Guard verification guys. (Did I mention
to you that there's a sea of small verification EDA start-ups vying for
your attention and dollars?) Esterel's new, though. I've never seen nor
heard of them before.
"* attended SynaptiCad/Synopsys Hands-on demo
This tool from SynaptiCad is not a mature tool, but does implement
Vera. The testbench is automatically generated for each test. I
have seen other verification systems that look better."
- Ed Strauch of Cirrus Logic
"SynaptiCAD: TestBencherPRO
Uses a reference model written in (Verilog, C++) to generate test cases
in "e", Vera, SystemC, C++, VHDL, Verilog."
- Monica Farkash of IBM
"Synapticad is a great company with a great product. I've been using
their TestBencher Pro product since about May. We are desinging an SOC
with about 40 cores, so verification is the biggest task in our
project. I picked this tool because it generates reusable system level
test benches. We needed to generate both C++ (using Cadence's
Testbuilder) and Verilog test benches, and we are able to do both from
the same set of timing diagrams. The Synapticad product builds a test
bench composed of several components: a test reader/transaction manager
that reads transaction calls (from a file in my case, but other sources
are possible) and initiates the transactions, a transactor model for
each timing diagram, an emulator module that models the system at a
behavioral level (we use C++ here because we have a lot of encryption
primitives, and the C++ code is much easier to come by) and a checker
that compares the results from the emulator and the model under test.
Most of the code is automatically generatedby Synapticad, even stub
functions for the behavioral emulator model. The only code we write is
the behaviroal code for these stub functions. The test script is just
a simple formatted ASCII file with the transaction input data, and this
is automatically transformed into a test reader by merging data into
the timing diagrams.
The other nice thing about TestBencher Pro, is that it is really great
for unit-level testing. If you need to just take a quick look at a
model, it can extract all the signals and create a quick test bench.
I was able to create a testbench for a successive approximation
behavior model in about an hour, including the time it took to figure
out how to use the program.
Synapticad gave us on-site training, and unlike many companies which
offer a canned training script, they used our OWN modules and worked us
through a real testbench, including testbuilder integration."
- Jay Abel of Shera International
"4.3 SynaptiCAD - TestBencher Pro
SynaptiCAD was founded in 1992 to provide affordable, high-quality
timing diagram editing tools. Since that time, they have expanded
their product line to include: VHDL & Verilog test bench generation,
timing analysis, stimulus generation, DataBook documentation, and
Verilog simulation. They currently have 5 products and 25 employees.
TestBencher Pro was first released in 1996. They are partnered with
Agilent and Tektronix, for purposes of interfacing their tool with lab
logic analyzers.
The main feature of TestBencher Pro is graphical test bench generation
for VHDL and Verilog. I saw a simple example of this tool on the
exhibit floor. The company did not have a demo suite. The interface
is very much like TimingDesigner from Forte Design Systems. The
difference here is that when you done drawing your timing diagram,
TestBencher Pro can produce a VHDL or Verilog BFM which generates the
desired stimulus for your DUT.
Timing can be cycle- or delay-based. The tool allows you to create
complex data structures which can be used to supply or store state
information. Markers for control and looping are supported. Sample
parameters generate self-testing code that is used to store and verify
data produced by the system being tested.
I think this tool would appeal to hardware designers who need to
quickly throw together a testbench to verify a bus interface they are
designing, especially if they have been designing based on an existing
timing diagram. However, I think the usefulness of this tool
diminishes when standard BFMs already exist, or there is a separate
verification team who can develop these models. In other words, the
tool might appeal to a designer who doesn't want the overhead of a
higher-level verification environment (i.e. Specman) yet doesn't want
to have to code up a Verilog or VHDL BFM bit-by-bit.
A parallel tool, DataSheet Pro, uses the same timing diagram editor,
and combined with project management capabilities, forms an environment
for creating and maintaining component datasheets."
- Jim Reisert of Paradigm Works, Inc.
"Forte: 'Perspective'
As far as verification tools go, the most interesting to me is still
the concept behind Forte's Perspective, and as I'm told TransEDA's
VN-Property DX. The idea is that you define (using temporal
expressions) various properties that you want to measure in your
system, like "how many times does event x follow event y by z
cycles", and the tool gathers the statistics for you as you run your
simulations. Can use this to check that your test suite is really
exercising the cases that you want, to answer the question "is my
verification really done, according to the block spec/test plan".
Unfortunately, we tried out Forte's Perspective and had mixed
results -- it didn't seem to be production worthy yet, but I know
they're working on it."
- Kris Monsen of Mobilygen Corp.
"Haven't checked out Specman, Vera or Superlog. One verification set I
looked at fairly hard was Forte's. It looked very promising but the
rest of the crew here is more comfortable with our home-built system,
so I wasn't about to push Forte's tools too hard."
- Mark Wroblewski of Cirrus Logic
"Esterel Technology applies formal techniques to the system design
level, using their language which is "esterel". They do transaction
models in esterel (text or graphical). They say their language is
designed for reactive systems, handles complex control flow well, and
is more deterministic (reader independent) than C. The output from
the Esterel tools a sequence of all possible transactions, which the
user can manipulate to other formats (would be handy if their tool did
the manipulation - maybe they should talk to Source 3)."
- John Weiland of Intrinsix
"Esterel Technologies presenting: Esterel Studio V3.1
Esterel is a sound old language, tested in about 50 years of usage in
describing reactive behaviorals in avionics, for building parallel and
hierarchical state machines. Limitations? you can express only safety
properties.
Esterel Technologies are based on this language. I saw an efficient
test generator for SoCs that automatically generate "C" tests. The
language is there, it is being used, their tools offer salutary
services to companies that already use Esterel."
- Monica Farkash of IBM
"Esterel's system validation concept looks interesting, but I haven't
sold myself on their methodology yet."
- [ An Anon Engineer ]
"Esterel and Real Intent look interesting. We'll probably investigate
next year."
- [ An Anon Engineer ]
"Haven't heard much of Valiosys Improve-HDL or Silicon Forest. Are they
US only at the moment?"
- Tom Fairbairn of 3Com Europe
"TNI-Valiosys sells a property checker with an emphasis on bug tracking.
They say it takes only 2 days to learn, and uses their PEC (Property
Environment Constraint)."
- John Weiland of Intrinsix
"TNI-Valiosys
At TNI-Valiosys I saw "ImproveHDL", which is a Model Checker, a
co-simulator called "Cosinate", and two reverse engineering tools that
take you from Gate Level to RTL respectively from RTL to SystemC.
I remember the reverse engineering tools as interesting, especially
because they support the idea of taking advantage of working at higher
levels by climbing up the levels and co-simulate."
- Monica Farkash of IBM
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