( DAC 02 Item 6 ) ----------------------------------------------- [ 9/10/02 ]
Subject: Atrenta SpyGlass, TransEDA VNCover, Verisity SureLint, Novas
CATCH THEM BUGS EARLY: It seems that the linting/debugging/code coverage
business has settled down to a few key players. Atrenta's SpyGlass seems
to own the Super Linter market (even though they don't like to call their
tool a linter.) TransEDA and Verisity's SureLint seems to own the Standard
Linter market, and a couple of people were interested in Novas new debugging
tool called Verdi.
"We've looked into SpyGlass after one of our people saw them at DATE
this year. It looks interesting but the question is does the effort
produce sufficient results? Or will the existing linting tools evolve
to do something similar? We're "wait and see" on this whole class
of tools at the moment."
- Tom Fairbairn of 3Com Europe
"We currently use Spyglass. The tool needs to mature, but we like the
ability to get "under-the-hood" in Perl. TransEDA's unified coverage
looks interesting from an assertion-based verification standpoint."
- [ An Anon Engineer ]
"I've been using Atrenta's SpyGlass 3.1 for the last couple of months
and have had reasonable success with it. Their fast-synthesis engine
that creates the structure used in their 'predictive analysis' was
particularly impressive, as was the number of rules that come with the
basic product. I was able to synthesize and analyze a 500 K gate
design in about 30 minutes. The schematic & hierarchy viewer has made
inherited RTL code easier for me to understand and easier to sift
through design errors. I can see how the tool can make RTL code
hand-off more efficient for design engineers. I had some difficulties
importing VHDL libraries but careful scrutiny of the documentation
solved my problems. I only used their tech support once and got a
quick response. I haven't tried to customize my own rules, so I
haven't much experience with their PERL and C interface. Using
SpyGlass, so far, has been a solid experience."
- Ehab Mohsen of Aptix
"A tool like Atrenta's SpyGlass I would rather call RTL analysis or even
physical analysis tool. For this specific tool I really see a need as
the sign-off seems to move from netlist to RTL and as a front end
designer I need a feedback about how my block will run smoothly through
the backend. On the other hand Atrenta is a single point solution and
I would like to see such kind of checks and analysis incorporated into
the hierarchical floorplanner or virtual silicon prototype tools (these
tools have such capabilities built-in but maybe not to the same degree
as SpyGlass.)"
- Raimund Soenning of Philips
"We have just started using Atrenta's SpyGlass and I must tell you John,
this tool rocks. I love it. We have used other linting tools in the
past but they produce 1000's of warnings which no one ever has time to
really throughly check. SpyGlass is more than just a pure linting tool
and is really helpful to me when a piece of 3rd party IP is thrown at
me and I have no clue as to what the clock domains are and what the
hierarchy looks like. SpyGlass is really good and best of all, its
very intuitive."
- Himanshu Bhatnagar of Conexant
"I worked with Atrenta's SpyGlass for some time. This year's version is
better than last year's one, but the Ispy they produce is still not
worthy for use. For big designs it just HANGS!!! And you cannot stop
it at all!! And above all Ispy is full of bugs."
- [ An Anon Engineer ]
"The Atrenta salesman would have a cow about having his tool stuck in
the linter category, since he went out of his way to emphasize their
Spyglass tool is NOT a linter; it's a "predictive analyzer". It
actually does a synthesis to generic gates and also has a built-in
cycle-based simulator that works behind the scenes, so can do things
a normal linter cannot (like checking for controllability and
observability, or checking whether tri-state contention can ever
occur). Last year it had 1,500 built-in rules, this year it has 2,500.
You write rules in C or Perl. Atrenta clearly wants to be designated
as a gatekeeper tool for RTL handoffs. They wrote rules for Xilinx,
Agere wrote a set for their customers and Altera is doing the same.
They also did a set of rules for VCS, which is interesting since
Synopsys owns VCS and their competitor Leda.
Tera Systems sells a design planner (or virtual silicon prototyping or
whatever else you want to call it) that has some linting capability.
It doesn't sound competitive with serious linters, but I don't think
it's intended to be. I think they want to be a gatekeeper tool and
understand they need at least basic linting capability to do that. I
don't think they can check for Reuse Methodology Manual rules, but that
doesn't matter for a gatekeeper anyway. One thing I didn't check out
was testability rules; this is something a gatekeeper tool should have.
The fact that they can check area and timing, as well as provide a
block level floorplan, gives them a natural advantage over a linter
for the gatekeeper function.
Synopsys bought the French company Leda for their VHDL and Verilog
linters. I've used these tools - they're easy to use and pretty good.
They sell a separate "specifier" tool to create your own rules, but
you really don't need it; without it you can still specify the polarity
of your clocks and resets, all the naming conventions in your RTL, etc.
Xilinx and Altera have rules for this linter, so they also seem to be
going after the gatekeeper position. Synopsys has apparently reduced
the price of this tool recently, which may be the reason Atrenta is
proclaiming they are not in the same category as Leda.
TransEDA sells a programmable linter for VHDL and Verilog. I really
like TransEDA's code coverage tool. It's sometimes quirky to set up,
but it's very intuitive to use - most designers just do the tutorial
and you're off and running in half a day. They also have a tool to
help you prioritize which test benches you should run first when
running regression suites. New for this year is support for IKOS and
Axis emulators - their coverage code instrumentation must be
synthesizable I guess.
Verisity sells a Verilog code coverage tool called Surecov.
Bridges2Silicon sells something like a code coverage tool. They
instrument your RTL code to add hardware for debug, and then you
synthesize it (probably for FPGAs). You then run the FPGA prototypes,
and the company's software can track exactly what lines in your
original RTL has been exercised in our hardware - sounds like a lot
of hardware is added for instrumentation."
- John Weiland of Intrinsix
"Novas Verdi.
Shopping for debugging tools is a bit like shopping for a TV - they
all show the same channels, all you have to do is pick the one with an
amiable menu and the best colors. Right?
Wrong in the case of Verdi because Verdi is an ... interactive TV.
It does everything that the others are known to do plus an extra: it
uses symbolic simulation (as in formal methods) to interactively step
forwards and backwards from a given point found via simulation. It
doesn't show only what "exists" but also what could be.
Not only is it a very nice example of combining formal methods with
simulation tools, which is soothing for everybody out there that
invests in formal methods in a way or in another, but it is a very
attractive tool by itself."
- Monica Farkash of IBM
"4.3.1 Novas Verdi
Market leader NOVAS introduced an addition to their well-known debug
system Debussy - called Verdi. It is what they call a behavior-based
debug system.
Verdi has some new features making tracing signals to the root of an
error more easy i.e. it visualizes all transitions which lead to a
faulty transition in a certain register graphically and also back over
time. There are two possible windows. The first just shows register
transitions on a time axis basis, the second dives into the logic cones
between registers. Verdi differentiates and highlights datapath
from control.
More important even: Verdi allows you to play with "what-if" scenarios.
Either you change the values at the root and look at the new result at
the faulty point or you enter the value you would expect at the faulty
point and Verdi calculates back what the root needs to be to obtain
the expected value (the terminology of Novas for this is 'source' and
'target').
Side Note: VHDL version of Verdi in Q4 - 2002 in beta available."
- Raimund Soenning of Philips
"We have the Novas lint but we only use the old Verilint features. I
haven't looked at the full suite. I used HDL-lint at a different
company, and it seemed very equivalent to basic Verilint - but much
cheaper since Avanti hiked the price. Neither tool is that great,
especially the documentation, but they're better than nothing. I'm
a big fan of syntax linting. Advanced analysis tools would have to
be proven - it's the old problem that it would be nice but if it's
not really helpful, it's not worth the bother to learn, run, and
maintain."
- [ An Anon Engineer ]
"We use Novas nLint. Seems to do the trick at a much lower cost than
Avanti wanted for VeriLint."
- [ An Anon Engineer ]
"TransEDA
TransEDA has a collection of EDA verification products. Interestingly,
they were listed as the number 4 company to visit by Dataquest. As a
result, they were a bit busy at DAC. One of their currently hot tools
is a coverage tool that uses purely synthesizable constructs instead of
PLI. As a result it can run on emulators. Mostly, TransEDA has a set
of tools that are focused on verification. They are trying to provide
a rounded-out set of tools concentrating on verification and analysis."
- Andy Meyer of Zaiq Technologies
"We are using VNavigator from TranEDA. Their 'not covered' conditions
are sometime quite hard to analyze, but apart from this, Vnavigator is
easy to use even for a newbie."
- Pascal Gouedo of STMicroelectronics
"We are using TransEDA sparingly. Their tool works well and is fairly
reasonable in price. Our problem is to get more of our designers to
use the tool."
- [ An Anon Engineer ]
"We use the TransEDA coverage tool and find it useful. It is part of
our design methodology to achive close to 100% coverage at the
block level."
- Mehran Bagheri of Multilink Technology
"For code coverage I have to stick to TransEDA VNCover as we are VHDL
designers. It's a mature tool and one should definitely collect
coverage during verification."
- Raimund Soenning of Philips
"TransEDA? We use it, it works. However we may want to consider
ModelSim's tool when it is complete.
Novas? We use it, we like it, it is useful for debugging. However,
ModelSim is rapidlly catching up with Novas. We may want to compare
cost/benefit of the two tools."
- Ed Strauch of Cirrus Logic
"I am quite pleased with my company's one perpetual Verilint license,
purchased back in the day from interHDL, and shared by 5-10 RTL
designers. I run Verilint early and often in the design process. It
is our first line of defense against bugs & prevents most stupid bugs.
I am pleased with the now-built-in, now-easy-to-use CoverMeter feature
of VCS 6.1. It has given me better visibility into how thorough my
tests are. Since better visibility leads to better design, CoverMeter
in VCS 6.1 ranks as my favorite EDA development of the past year."
- Jonah Probell of Lexra, Inc.
"Verisity SureLint has always been a cool coverage tool."
- Cliff Cummings of Sunburst Design
"Surelint is cheap & it works. Atrenta is really not a linter; it's a
design-analysis tool (clock domains, longest logic-paths.) It doesn't
catch things Surelint & others do, and does things linters don't do."
- [ An Anon Engineer ]
"Surelint still appears to be the most feature rich and easy to use
linter. Too bad its being dicontinued. No other tools matches the
ease and flexibility in filtering which is so important in eliminating
all the ASIC library foo and other foo caused my 3rd party IP and
RAMs in our designs."
- Sean W. Smith of Cisco Systems
"We use Avanti's RTL explorer. It will have you writing code your
grandmother can parse if you don't draw a line in the sand. There is a
challenge in our company to write a parameterizable synchronous counter
that doesn't generate errors. Unfortunately, the shortcomings are more
from Verilog's loose specification than the hyperactive scrutiny of
ExploreRTL. In general, though, I'd have to say it is a valuable tool
for improving the overall quality of your RTL code."
- Jay Abel of Shera International
"Avanti ExploreRTL for RTL checking is showing its age. I don't think
it has been enhanced much or is well supported. Some ASIC vendors are
shipping tools with some similar capabilities in their design kits."
- John Busco of Brocade Communications
|
|
