( DAC 01 Item 39 ) --------------------------------------------- [ 7/31/01 ]

Subject: Artisan, Virage, Nurlogic, Library Technologies, Virtual Silicon

NOT HOME GROWN:  If you don't want to use your fab's lame libraries, but you
also don't want to go through the trouble of making your own libs/memmories,
then you'll be looking at Artisan, Lib Tech, Virage, Nurlogic, and Virtual.


    "Virage Logic
     ------------
     Virage appears to be pretty much the standard memory provider for COT
     libraries.  They provide compilers and hard macros for standard and
     Mega-bit SRAMs.  If I'm not mistaken, Virtual Silicon and Artisan both
     are beginning to default to Virage memories.  They have 1- and 2-port
     memories and a 2-port register file.  Multi-port memories are under
     development.  They have UMC 0.18um and 0.13um memories.  Their
     dual port memory uses a Virage bit cell.  Both the 1-port memory
     and the 2-port register file use a foundry bit cell."

          - [ An Anon Engineer ]


    "Memory Compilers and Models

     Virage has their usual selection of compilers for RAMs, ROMs, CAMs,
     etc., and they are reselling the Atmos compiler as well. Their RAMs now
     have BIST and redundancy like the Genesys BIST, but the repairs can
     either be done via laser at the fab or you can do soft repairs in the
     field. TSMC recommends redundancy on any RAM over 1M.

     In addition to their free libraries, Artisan provides basic RAM and
     ROM compilers.

     Atmos sells RAM Compilers for embedded applications. They currently
     support TSMC, NEC and UMC. They output VHDL, Verilog, LEF, .lib and
     GDSII.

     Virtual Silicon sells unique RAM compilers for UMC. They also have a
     PLL compiler.

     Mosys sells one transistor SRAMs designed for TSMC, UMC or Charter.
     These are not generators, they are instances with specific sizes. They
     say the one transistor SRAM is 2X to 3X denser than normal SRAM and
     uses only 1/4 the power.

     Silicon Design Solutions sells SRAM, CAM and FIFO compilers for LSI,
     Silterra, TI, TSMC and UMC.

     Bluewave Technology represents Seiko Instruments, who have a memory
     design system for memory designer. It does floorplanning, place and
     route and compaction, which they say provides superior results to
     simple tiling.

     Denali sells C-language memory models. They say their models take very
     little actual space (important if you're simulating, say a memory
     board) and have a lot of built-in checks like overwriting data without
     reading it and reading from locations you haven't written to yet, or
     even checking that linked lists look right. Their tool now integrates
     with Novas's Debussy to allow people to view memory contents on the
     waveform viewer."

          - John Weiland, Intrinsix


    "I would say Artisan has only a small niche to fill.  I don't think
     they have any vision to expand beyond basic libraries and memories,
     so I wouldn't expect significant growth there."

          - Bill Cox of VI ASIC


    "Nurlogic
     --------
     Nurlogic has 67 employees in San Diego.  80% of this headcount is
     design and development.  They have 0.25um and 0.18um UMC libraries.
     0.13um is under development.  They don't have any libraries at all on
     any supplier for 0.35um.  They offer license-based libraries (rather
     than 'free' libraries like Virtual Silicon).  Their licenses are for
     single or full use.  Below 0.18um, they have a high performance and a
     high density library.  The high performance library is 10-30% faster
     than the high density library.  They have a small design services
     group but tend not to emphasize it unless customers really, really
     need it.  Would be very interesting to understand the differences
     between the Nurlogic and Virtual Silicon 0.13um UMC high performance
     libraries."

          - [ An Anon Engineer ]


    "Mehmet Cirit (Library Tech) has a brand new idea - constant-delay
     cell libraries for logic synthesis.  He's full of new ideas.  I've
     read his  white paper several times, and I still can't figure out how
     anyone would get it to work.  If the cells have constant replacement
     delay (the next-larger cell has the same delay for its higher load
     limit) then where's the timing optimization?  And how well will P&R
     tools handle a netlist where *every* net has a routing constraint?"

          - [ An Anon Engineer ]


    "Library Technology, Inc. sells library characterization software, but
     can also create new cells on the fly to solve timing problems. Unlike
     Siliconcraft, they don't do layout.

     Viscid can create libraries or expand libraries from vendors like
     Artisan, etc. to get speed for new operating conditions, etc. They
     also have a library consistency checker to see that all your different
     models are consistent - Lord, have I needed one of these in the past."

          - John Weiland, Intrinsix


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