( DAC 01 Item 38 ) --------------------------------------------- [ 7/31/01 ]
Subject: Silicon Metrics, Cadabra, Numerical, Circuit Semantics, InnoLogic
HOME GROWN LIBRARIES: For some odd reason, Prolific standard cell gen users
tend to be Circuit Semantics characterization users -and- Cadabra std cell
gen users tend to be Silicon Metrics characterization users. Why? I don't
know. Customers just like to match up these 4 different vendors tools this
way. The news in this niche this year is that Cadabra's gotten much better
and was aquired by OPC biggie, Numerical Technologies. Also this year users
seemed to write a lot more about Silicon Metrics than Circuit Semantics.
"Cadabra was acquired by Numerical Technologies. They produce layout
libraries from sized netlists provided by the user. They do not use
generators; they place and route transistors."
- John Weiland, Intrinsix
"I continue to watch Numerical Technologies with great interest. Their
tools offer something of fundamental value. The key question is
whether their tools will become essential for in-house COT-shop use
or whether they'll be relegated to use only by foundries. That's still
not clear at this point."
- Mike Carter of Mosaid Technologies
"Numerical Technologies is neat stuff, but I don't expect it to be
integrated into routers the way they are suggesting, so I think their
market is also limited."
- Bill Cox of VI ASIC
"Cadabra seems like it is ready for prime time... finally."
- [ An Anon Engineer ]
"The Taurus tool from Avanti will do the OPC and their new Venus tool
will check it, and I saw some smaller company that has a tool that just
does checking, but I'll be darned if I can remember who they are. I
don't know if Cadence or Mentor have similar products.
The tool from Numeritech (Numerical Technologies) and also Taurus tool
from Avanti will check for illegal geometries and add phase shifters.
The Numerical Technologies tool is also integrated into Cadence Assura.
I didn't get to check out Mentor for similar tools, but I know they
have a tool for phase shifters, too.
All of these tools are only dealing with polysilicon (gate level) at
present. Since poly is typically used only within cells, this means
that you can run their DRC on individual cells, and if the cells are
clean it's unlikely you'll have problems at chip level. Dealing with
metal levels is another story. It's not clear to me who will solve
this problem - routers when they design the metal, compactors/expanders
like Rubicad or Sagantec after the routing is done, or someone like
Numeritech, Avanti or Mentor when you go to make the mask.
I believe Numeritech is working with Cadence's Place and Route
researchers, and I'd assume Avanti has something in the works for
their router."
- John Weiland, Intrinsix
"The Cadabra series of software is even nicer than before but has a
limited usage for Standard cell libraries developers. Would be nice to
be able to use such tool for all purpose analog layout."
- Dan Clein, PMC-Sierra
"The most promising tool in memory timing characterization - Silicon
Smart-MR from Silicon Metrics. Uses simulators such as HSIM or
Nanosim for setup, hold, access and cycle time measurements, power
measurements. Uses a Synopsys template file to insert values from
the simulation results."
- Raj Sayana of MoSys
"As for library characterization, just about everyone who has ever done
a library (me among them) has created a script to automatically chew on
the SPICE results and put it into a Synopsys format (and whatever
else). Companies like Library Technology and Silicon Metrics have sold
their scripts for years, but have always seemed to me to be a solution
in search of a problem. They have a hard time supplanting people's
home-brew scripts that do exactly what they want.
Last year they started talking about resizing drivers for speed and
doing better timing analysis - I think they might have found something.
The SPICE-like analysis tools from Siliconcraft can actually modify
your netlist to optimize for speed and power. It does this by creating
additional cells in your library (possibly hundreds of them) with
different drive strengths. Note that this assumes your golden STA is
their own SPICE-like one - don't know what your foundry would think
of this."
- John Weiland, Intrinsix
"Silicon Metrics
---------------
67 employees based in Austin, Texas, focused on cell library
characterization and commercialization of OLA (real-time delay
calculation). The real-time delay calculation is embedded in a
product called Timing Sign-off (TSO). TSO hooks into a static timing
tool (like Primetime or Ambit PKS), so you still run normal static
timing, but instead of bringing in an SDF or running a non-signoff
delay calculation, TSO performs golden delay calculation (plus a few
other nifty things).
Here's what Silicon Metrics adds on top of OLA:
1. Instance-based voltage de-rating.
PrimeTime is starting to offer voltage islands for analysis of
different voltages intentionally designed into a part. TSO is
offering instance-based voltage de-rating to account for
unintentional voltage differences occurring across the die. These
instance-based voltages are back-annotated from Simplex (not quite
sure on the mechanism).
What was also interesting about this demo was the rabid interest
from designers already working in <=0.15um technologies. Voltage
drops are so design- and metal-dependent that it is difficult to
predict until you have some design collateral, but it does make me
think we may need to put more emphasis on this for the process
technologies we're RFQing now.
2. Automated critical path simulation
Based on PrimeTime path analysis, TSO will spit out paths for HSPICE
simulation. Parasitics go out through DSPF or you can plug in field
solution (if you want high accuracy on something like a clock).
Instance-based voltage gets sent out to SPICE as well. They will
kick off SPICE on multiple CPU's. SPICE results are back-annotated
into PrimeTime run.
3. Reduced/compiled parasitics output to binary for linking into STA.
Need to think about this more to determine the true value. The 2
purported benefits are:
a) faster read than sdf because its binary.
b) for ECO's, could do incremental delay calculation on only
the impacted part of the design.
Some other tidbits
- It became obvious to me that incrementally linking delay calc
results into STA makes it really difficult to tell what
conditions/changes you have/have not included. TSO provides an
capability to track the history of what's been linked into a
specific STA run (kind of like keeping track of what you've put
into an SDF).
- Silicon Metrics also has a stand-alone delay calculator that they
claim is within 3-4% of SPICE. This delay calculator does not yet
take cross-cap into account.
TSO works with 2000.11 version of Primetime and an engineering version
of Ambit PKS."
- [ An Anon Engineer ]
"Silicon Metrics - pretty good flow and nice point tool substitute.
Since Mastertool box has pretty much been obsoleted in the market
place, they are the only game in town that is programmable enough for
the new complex waveform suites for the 0.13 and 0.10 libraries. You
can also spin the product to support complex cells in addition to std
cell blocks. This is a good thing for guys who buy IP and then end up
with legacy blocks from a design provider that is no longer in biz."
- [ An Anon Engineer ]
"Mem characterization sounds stupid unless you do custom memories.
Still you can guess what I think of the memory suppliers out there
when I say that I think the memory characterization guys should do
pretty well. We use Legend."
- John Szetela of AMD
"We use StarXT and StarRC. Works fine for us."
- Phil Hoppes, Intersil
"Circuit Semantics & Silicon Metrics both demo'd memory characterization
tools, but both are still green."
- [ An Anon Engineer ]
"We've not had good luck with any layout migration/generation tools.
Circuit Semantics seems to work pretty well."
- [ An Anon Engineer ]
"Prolific Inc.
-------------
Two things of interest:
1. Just worked with Virtual Silicon to produce a high performance
UMC 0.13um cell library.
2. Working with Virtual Silicon and Monterey (?), they've developed
something they're calling liquid libraries that enable run-time
generation of library cells custom-sized for specific paths and
timing problems. By customizing transistor-sizing/-ratioing
to a specific timing problem (rather than just adding buffers),
it should produce better timing with lower power than just
moving to the next power of cell. Don't know how the whole
thing works yet, but its an interesting concept."
- [ An Anon Engineer ]
"Silicon Metrics also sells library characterization software. They can
take temperature and voltage data from Simplex and create instance
specific characterizations of cells in your design, so that do don't
have to assume that all cells across the whole chip are at worst case
voltage. Note that Iota does something similar to the Simplex/
Silicon Metrics team.
Prolific sells layout generators for standard cells. They use multiple
small generators for larger cells (e.g. 3 or 4 for a flip flop) and
then do compaction at the end. This allows easier creation of new
generators by the user."
- John Weiland, Intrinsix
"The most promising tool in memory logic verification - ESP-CV symbolic
simulatior from Innologic makes *complete* coverage in logic
verification possible. It could automate the Verilog netlist creation
for our 1T-SRAM creation using a configuration file."
- Raj Sayana of MoSys
"Innologic
They sell a PLI that will turn your ordinary Verilog simulator into a
symbolic simulator and can also add formal verification capability.
Those of us who have done custom test or initialization protocols with
Synopsys test tools are familiar with symbolic simulation. In addition
to signals taking on values of "0", "1", "X" or "Z" they can take on
any arbitrary string as a value. If you have an AND gate and the inputs
are "0" and "1", the output is "0", just like an ordinary simulator.
If the inputs are "A" and "1", the output is "A". If the inputs are "A"
and "B", the output is "A&B". If you have a lot of symbols, signal
values can turn into big, ugly equations, which can get uglier with
each new clock cycle. People weren't expecting a tool like this and the
A.E.s didn't seem to know how to explain it (sounds like 0-in a couple
of years ago).
I talked to some people who saw the demo; they were doing the
smile-and-nod thing during parts of it. It took me three trips to sort
of get it. The A.E.s had no good examples so I am going to make one up,
which may or may not be right. Suppose your design has to accept
packets of variable length, and you want to verify that you will never
accidentally store header information in the data registers or vice
versa. Your testbench can be ordinary except that the bus can take on
values of "header" or "data". Your registers will start as "X" but will
then take on values of "header" or "data" as time goes by. You can now
test the data register to see if it ever takes on a value of "header"
and also check the header register for "data". Pretty nice, but you
still have to go through all sorts of combinations of control
bits/signals to try to make it break. Now give symbolic values to the
control bits/signals as well. Instead of the registers taking on simple
values of "header" or "data", they will be equations in terms of those
two values plus all the control signals.
The equations can tell you what will happen for all possible values of
the control signals, for however many clocks you have simulated, and
with whatever "0" and "1" values you've put on other lines (in this
example, I believe the length information for the packet would have
to be binary to be compatible with the number of "data" words being
supplied by the testbench). If the equation stored in the header
register has a term with "data" in it, you now know it is possible for
data to get into the wrong register. They say their formal verification
tool will give you the simplest possible example of how data can get
into this register. They say they use very clever BDDs to allow signals
to take on really big equations as values, but if you use enough
different symbols for enough clocks the tool will run out of steam.
Note however that since you are checking for all possible values of
the pins with symbolic values on them, your simulation may be much
shorter to effectively check your design. They say they can check a
RAM in only four cycles (two write, two read).
Two years ago it took me several visits to understand what 0-In did;
just like Innologic this year."
- John Weiland, Intrinsix
"Innologic looks intersting. It's a niche market right now, but their
core technology may have some other nice applications."
- [ An Anon Engineer ]
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