( DAC 01 Item 30 ) --------------------------------------------- [ 7/31/01 ]
Subject: 'Hidden Dragon', Silicon Perspectives, 'Integration Ensemble'
EVERYBODY'S PROBLEM: The one embarrassing problem that PhysOpt/PKS/Magma
all share is they're each missing a good hierarchical floor-planner. Let's
say you're making a 2 million gate chip. You'll need such a floor-planner
to break up your design into 100 K to 300 K gate blocks, because that's the
most gates PhysOpt/PKS/Magma can synthesize.
Cadence is working on this problem with its 'Integration Ensemble' tool, but
they openly report that it won't be ready for another 15 months (Q3, 2002).
Magma just announced at this DAC their fix to the floorplanning headache, but
it's uncertain whether it's quite beta or even alpha code quality right now.
Synopsys thought they had this problem licked with their Chip Architect
tool. A few users have actually reported successful tape-outs with Chip
Architect, but most others reported:
"Chip Architect has all of the ills associated with doing floor-planning
hierarchically. Strict hierarchical approaches divide the die into
non-overlapping regions with logical and physical bounds necessarily
the same. Doing this limits the floor-planner's ability to move cells
anywhere on the chip. I/O cells, hard blocks like RAMs and cores,
clock buffers, and repeater buffers tend to have strong physical
constraints and need to be placed anywhere on the chip regardless of
of their place in the logical hierarchy. Because of the strict
physical constraints on these blocks one solution is to put cells like
I/O cells and hard blocks at the top of the hierarchy. Doing this in
the logical world makes the interconnect a mess. Changing the
hierarchy in the physical world, which Chip Architect can do, messes
up the formal verification. The presenter did not have an answer when
I questioned the impact on Formality, but one of the users in the
audience was clear that Formality could not handle the changes in the
hierarchy and I don't think Chrysalis can either.
Without a lot of scripting to reserve space in blocks for logic from
other blocks, it is not clear that Chip Architect is usable to do the
type of floor planning we have traditionally done."
- Ken Merryman of Unisys in SNUG'01 #8
"We have a copy of the Chip Architect tool and have attended the
training sessions. While they loudly tout that it supports
hierarchical placement, what is really true and mentioned offhand
by John Stahl is that it can ONLY do separate placement on each
and every hierarchical block.
That means that even DesignWare inserted levels of hierarchy must be
physically regioned on the die if left in the netlist. This is
absurd for large designs with hundreds of hierarchical instances!
You can only run placement starting with lowest levels of hierarchy
and work up. No logical/physical variation is allowed, which is just
a downright odd choice for a company who sold Floorplan Manager
suggesting that you regularly encounter logical/physical mappings."
- Thomas Ayers of Believe, Inc. in ESNUG 364 #1
Even the guy who did the first customer review of Chip Architect (Jon Stahl
of Avici) later wrote into ESNUG *retracting* his endorsement of Chip
Architect! (Which was a first. I've never seen something like that happen
before in the history of EDA.) This was ugly, Synopsys realized it, and
they started the 'Hidden Dragon' project to fix Chip Architect's problems.
Synopsys claims that 'Hidden Dragon' will be ready "in a matter of months".
Sticking their tongues out and mocking Synopsys/Cadence/Magma are Monterey
and Silicon Perspectives. Even though Monterey can't even get one customer
tape-out with their flavor of physical synthesis ("D'Oh!"), they were smart
enough to acquire Aristo IC Wizard last year -- an established block
floor-planning tool. And Silicon Perspectives 'First Encounter' (FE) is a
proven block floorplanner (and more) with a proven 43 customer tape-outs.
Taken together this begs the question: "As a chip designer, is your current
project willing to wait for 'Hidden Dragon'/'Integration Ensemble' (which
will have tight support with PhysOpt/PKS) or does it need FE/Aristo now?"
"Chip Architect is useful, but it has its problems. The GUI is
incredibly slow. We are not doing large SoCs in my group, so we
haven't had problems with the limited capacity of Chip Architect."
- Lars Bo Graversen, MIPS Denmark
"For RTL, we use Synopsys Design Compiler, not Magma synthesis. We
also placed the blocks of our design using Synopsys Chip Architect."
- Marco Montalti, STMicroelectronics from ESNUG 374 #7 on
using Magma BlastFusion for a tape-out.
"When we evaluated Chip Architect earlier this year. We were looking
for a good hierarchical floor-planner. We felt it had major
difficiencies in handling hierarchy especially for ASICs with area
I/O and a lot of RAM or cores, where floor plan regions need to
overlap. We met with Synopsys Corporate AE's and they seem to
understand the problems. Now we are looking forward to evaluating
Hidden Dragon, which we have been led to believe will solve some of
these problems. We aren't kidding ourselves. These are tough
problems, which will most likely involve changes in our design style
and hierarchy to make them work. That is our incentive to stay flat
as long as possible."
- Ken Merryman, UniSys
"Hidden Dragon:
Hierarchical Design Planning (Hidden Dragon) will address the classic
problem of hierarchical physical design: what happens when one of the
hierarchical blocks blows out of it's area budget? Hidden Dragon will
use a "Virtually Flat" view of the full chip, giving full visibiliby
into the sub-blocks. Their roadmap is:
- Provide full chip context for optimum macro placement, block
shaping and pin assignment.
- Use "Smart Clusters" to build extractions and provide 10X - 100X
runtime and capacity improvements.
- Use the PhysOpt placement engine for block and full chip
optimization.
They claim that this smart clustering technique would make a 2M gate
block seem like a 10K gate block in terms of runtime. Smart clustering
groups the logical hierarchy into highly connected clusters, but gives
full chip level visibility to macros regardless of their location in
the logical hierarchy.
I don't know if "smart clustering" would be able to create clusters
across major logical hierchical blocks (like truly flat timing driven
placement) or if it is still bound by the logical hierarchy.
"Virtually Flat" floorplanning places the smart clusters, determines
block shapes based on full chip context, adds a power plan, optimizes
pin locations, adds feedthroughs and repeaters, and outputs block level
constraints to drive PhysOpt.
They claimed that a 1M gate floorplan could be generated in 4 minutes.
The new Interface Logic Model (ILM) recently introduced in PrimeTime
will be supported and automatically generated."
- Bob Wiegand of NxtWave Communications
"Silicon Perspectives vs Hidden Dragon: At this point of time, Hidden
Dragon is unavailable to us even though we're using PhysOpt. First
Encounter (FE), however, was available for tryouts. We are currently
using it in our flow. Overall, we settled on FE->PhysOpt->Apollo
as our flow. I believe we gained quite some time using FE instead of
Planet to do our design planning.
Comments on Apollo Astro: To me, it seems like Avanti is in danger of
falling way behind in the race, unless they migrate to a more complete
solution. If things keep moving as they are, I could conceive of a
scenario within about a year, where we could go FE->PhysOpt->Hercules.
That's assuming SPC and Synopsys deliver on their statements. ;)
Currently, we're using FE for design planning/floor planning. SPC does
need to step up on its' products' stability, though. We're finding
FE needs to be used with lots of TLC. Minor usage mistakes causes
it to crash!"
- [ An Anon Engineer ]
"If I had to choose one of these flows today to tape-out then I would
go with Synopsys PhysOpt. I've heard great reviews of Hidden Dragon."
- [ An Anon Engineer ]
"Second hand (colleagues and friends) SPC is a production, stable, and
highly regarded tool. It also has some novel technology called amoeba
placement. I hear FE's primary purpose is as a "quick" floorplan and
timing estimate "virtual prototype" tool. It also earns major points
from me for running on Linux, thus giving it a 2x HW performance edge
over Planet, et. al.
We don't use FE, because our ASIC vendor (LSI) has an incredible amount
of infrastructure built around Planet and the Milkyway database, for
power planning, flip-chip redistribution routing, pad placement, etc.
Hidden Dragon isn't even slideware yet, and IMHO, the memo you received
looks like something Synopsys wanted to leak. For all it's promise,
Synopsys has made some major wrong turns on Chip Architect. And I can
tell you from first hand experience that the touted ChipArch/PhysOpt
"intergration" is at about alpha stability right now. It's unusable
in a real flow."
- [ An Anon Engineer ]
"I was very happy (amazed actaully) that the hierarchical layout tools
that LSI has just released are at least a year ahead of what Hidden
Dragon is capable of. As a result of all the Avanti happenings and
compatibility issues mentioned in ESNUG, LSI is qualifying
Monterey's Dolphin."
- Duncan Halstead, LSI Logic
"The other biggest lie I heard at DAC was 5-way. Monterey, Magma,
Avanti, Synopsys, Mentor (floor planning) all claimed to have closed
the deal to be the _exclusive_ next generation floor plan/APR/Cleanup
tool at LSI Logic. If you total all the biz for the 5 vendors - it
would mean LSI is spending $100 M in APR by Q4 of 2001. That is a lot
of money for a company in the red / on expense freeze and for
supporting a process not yet in production."
- [ An Anon Engineer ]
"I wouldn't wait for Hidden Dragon; Silicon Perspectives has useful
capabilities right now. But there's still a fundamental gap, to my
mind, between early floorplanning (pre-gate) and mid-game floorplanning
(gate level netlist exists). That applies to all tools currently in
the market. This is a critical weakness because early floorplanning
is essential in SoC design, most especially with physical synthesis
use. But that early floorplanning has to survive, in a graceful way,
the transition to gates. I'm not so worried about end-game
floorplanning (surviving late design changes); that looks manageable
with many of the modern tools, including Silicon Perspectives."
- Mike Carter of Mosaid Technologies
"The couple people who I know that did attend told me it was a boring
DAC. Most of the big announcements (Synopsys Clock Tree insertion
and Route66) we already knew about from our Synopsys apps guys;
although someone mentioned that the Hidden Dragon demo was very
impressive."
- Robert Cram, Gennum Corp.
"We use Silicon Perspective and have been very successful with it.
I don't know about "Hidden Dragon". Ask next year."
- John Szetela of AMD
"Synopsys PhysOpt worked well for us and we are continuing to use it on
future projects. (We are looking forward to the improved PhysOpt
integration with IBM tools.)
We're using Chipbench/HDP as our floorplanner so we don't have Chip
Architect. Silicon Perspectives came by a couple months ago and put
on a good show especially in the speed area. It had some nice features
and things but again was redundant with Chipbench/HDP in our flow.
Please excuse my ignorance but what is Synopsys 'Hidden Dragon'?"
- Christopher Gorzek, Cray Computers
"Cadence's 'Integration Ensemble' and Synopsys 'Hidden Dragon' are not
real yet. They all have pieces to show and the rest to promise. I like
Integration Ensemble's blueprint better since it is more integrated.
Hidden Dragon is the second time around after the lessons Synopsys
learnt from Chip Architect, so I assume pieces will be eventully built
better. But Synopsys is still not on single DB which means Cadence and
Avanti are ahead. Cadence will also have a second time around after
lessons learnt from Integration Ensemble and DFII, so a real integrated
SOC environment is not any time soon. InTime is in the same boat, good
flow but in-complete inplementation. The rest don't even understand
the whole problem yet.
Before Hidden Dragon and Integration Ensemble can really deliver,
Silicon Perspective will enjoy the SOC market for the next 1-2 years."
- [ An Anon Engineer ]
"Given the poor integration between EDA tools, Cadence Integration
Ensemble and Synopsys Route66 have bright futures."
- Bill Cox of VI ASIC
"Not impressed with Cadence's Integration Ensemble, especially when they
say it's not available until Q3 2002."
- [ An Anon Engineer ]
"I like the Apollo/Astro flow much better than Silicon Ensemble. I'm
intrigued by Plato's NanoRoute, but haven't seen it, yet. If CDN's
Integration Ensemble is ever released, I'll take a look, but I'm no
longer holding my breath."
- [ An Anon Engineer ]
"Both PKS and PhysOpt seem like they'll do an OK job on the block level
but both Synopsys and Cadence seem to have dropped the ball on
hierarchical design. Cadence won't have Integration Ensemble out until
Q3 '02 (after next year's DAC) and it seemed like PKS needs it to
elegantly handle alot of the hierarchical issues. I like PKS's close
timing correlation if you're using a Cadence backend, but I think its a
weakness that all arithmetic architectures (ie. ripple, CLA, etc.) are
picked based on wireload models and not the true placement. The new
Chip Architect (Hidden Dragon) will be available in a few months and
sounds good, but Silicon Perspective is worth a look. One definite
advantage of PhysOpt is being able to leverage all of your Design
Compiler optimization tricks."
- [ An Anon Engineer ]
"During the Monday editor's roundtable discussion, the EE Times business
editor reported that Sony and Sanyo, winners of the gold and silver
design awards, both said that they wished they had had better
hierarchical design tools than the ones that they used.
This is an interesting comment given that Silicon Perspective was used
on both of these designs."
- [ A Monterey Employee ]
"There are quite a few vendors offering tools for 'design planning',
the goal being to reduce the number of iterations between RTL and
place&route. Ranked in order of most interesting/popular (as far
as I can tell):
1. Silicon Perspective: FirstEncounter
2. TeraSystems: TeraGates
3. Monterey Design Systems: IC Wizard (Aristo)
4. InTime Software: DesignArena and DesignWarrior (RTL analysis
and early floorplanning tools).
Also of note: Get2Chip's tool basically does part of this as part of
their top-down, high-capacity "topology-driven" synthesis. Their
"Topomo" tool breaks the design up into small (~10 kgate) chunks and
performs placement for them, feeding the extracted wire delays back to
synthesis and giving the "cluster" placement info to the P&R tools."
- Kris Monsen of Mobilygen Corp.
"SiliconPerspective -- their idea seems good let everyone else fight
over the APR space they will take all the placement/global route and
partitioning work and output PDEF and SDF to the "real" APR players.
This way people are not stuck or locked in to the whole Avanti/ Magma/
Monterey/ Cadence/ Synopsys flows. Big question - are these SPC guys
good enough to get people to believe that APR is just a point
tool again?"
- [ An Anon Engineer ]
"We evaluated Silicon Perspective and it is very impressive. Super
fast placement and high capacity. I sure wish ASIC Vendors would
support Silicon Perspective to make the hand-off question go away."
- John Busco of Brocade
"Silicon Perspective/FirstEncounter
First Encounter tool aimed at large designs, where top-level placement/
pin assignment choices are non-obvious. Focused past 3 years on
database technology, can handle large designs read in a 1M gate design
into tool in 3 minutes, *live* quoted ability to process 3M placeable
instances in under 10 hours does placement, routing, and extraction and
can show a congestion report based on routing (routing is not DRC-clean
today, working on it). They can critique the logical hierarchy, in
terms of its suitability for physical design / partitioning, good for
power/bus prerouting with cookie cutter ability, so the top-level
pre-routes can be pushed down to blocks ability to drive PhysOpt (via
PDEF) and Avanti (via dumpfiles). Tool runs on Linux"
- [ An Anon Engineer ]
"We're slowing evaluating PhysOpt. We have been successful so far
(no tapeouts yet). We expect to rely on PhysOpt in 2002, maybe 2003.
We're looking at TeraForm for RTL planning to help move to timing
closure more quickly. Silicon Perspective looks promising and we
have invited them in to take a closer look at what they have."
- [ An Anon Engineer ]
"As far as I know, Magma is the best. BTW, Silicon Perspectives does
help us solve problem efficiently."
- Jeong-Fa Sheu of Acute Communications
"* Silicon Perspecitve's First Encounter floorplanning tool looks very
impressive. They seem to have established themselves as the
best-in-class tool for top-level chip planning with many, many
customers and many, many tapeouts. In fact Cooley's report lists
First Encounter as having the 2nd most tapeouts behind PhysOpt
amongst the new breed of physical design tools. I thought Monterey's
IC Wizard looked comparable, but Silicon Perspective says it isn't."
- [ An Anon Engineer ]
"Silicon Perspectives
--------------------
Silicon Perspectives' First Encounter product appears promising as a
hierarchical layout solution. However, upon closer inspection it was
difficult to determine 1st Encounter's exact value-add to hierarchical
ASIC planning and re-integration.
What it does, and what I still wonder about...
o Timing constraint partitioning from chip-level constraints
- 1st Encounter propagates mcp's & false paths. Don't know
where PrimeTime is on that.
- Hasn't dealt with evil LogicVision timing constraints yet.
Since this is where virtually ALL of our timing constraint
problems have been, I can't help but feel they're still playing
minor league ball.
o Chip partitioning (but we only partition the chip once -- we have
to integrate it over and over -- what does this buy me on chip
integration?)
o Pin Assignment (legitimate value-add in that they can place
top-level pins with full visibility inside the blocks)
o Floorplan refinement based on rough route (but it's "1st Encounter"
routing, not sign-off routing -- so why wouldn't I just get out
to Silicon Ensemble and get real routing?)
They run this thing on a laptop, which did seem impressive."
- [ An Anon Engineer ]
"Magma and Monterey are the only comprehensive alternatives for 0.18 um
and below. We're concerned about Magma's financial viability. Silicon
Perspective is a useful stopgap measure to augment existing tools from
Avanti, Cadence, and Synopsys."
- [ An Anon Engineer ]
"We did our block level design using Magma (no "real tapeouts") that
were assembled them on the top level using Avanti for 2 reasons:
a) Magma didn't support hierarchical design which we needed due
to our configurable IP
b) Our current internal customer uses our internal plain vanilla
design flow and has to integrate our core in their system
and thus needs the Apollo Database anyway.
So we figure if we can integrate the Magma blocks into our Avanti
top level then our customer will have no problems integrating
this top level in their systems (just to be on the safe side.)"
- [ An Anon Engineer ]
"Monterey Design (Aristo) IC Wizard
----------------------------------
NEC is working to incorporate Monterey's IC Wizard (formerly Aristo)
into their hierarchical design flow. IC Wizard seems to play in the
same arena as 1st Encounter. Here's a rundown of what its got:
- Cell placement.
- Timing constraint partitioning.
- Global routing to drive pin placement and channel allocation.
- Rectilinear block support
- Distance-based buffer insertion.
- Power grid generation.
- Blocks come back in as hard macros. Does not appear to see
inside of blocks when re-importing them.
- No clock yet.
Overall, it didn't seem like much of a top-down/bottom-up hierarchical
design environment yet. Some good features, but just not well-
integrated yet."
- [ An Anon Engineer ]
"IC Wizard (Aristo) reminds me of something we did at SGI, trying to get
top-level placement and timing information early by feeding basically
completely empty top-level Verilog blocks, along with area estimates,
into the flow at the same time we were doing our RTL. IC Wizard can
create blocks for layout by abutment or with global routing. It can
start floorplanning with a scant top level netlist and a whole bunch
of estimates.
The tool is written in native 64 bit and is multi-threaded. There is
no Linux support. They recommend 1M Gate blocks which will give
overnight runs for Sonar and P&R."
- [ An Anon Engineer ]
"Avanti Jupiter is an excellent floorplanning tool, but Saturn has very
mixed results. Astro - it's too early to tell.
First Encounter is excellent - we have groups using it successfully
right now. I hope that Hidden Dragon lives up to its promise, since
the industry needs compeition."
- [ An Anon Engineer ]
"Prosper Design Automation
They sell an interesting tool for block level routing. When you route
your blocks, you bring each port out to the periphery of the block,
but you inevitably wind up with some that you wish you had placed
elsewhere. Their tool moves pins to allow standard routers from
Cadence or Avanti to route into the guts of block, then it takes
the part of the route that is physically inside the block and moves
it down in the hierarchy so the pins are again at the boundary again,
but now in an optimal location. The tool does not actually do the
routing. They had the most poorly thought out giveaway - a size 40
men's belt (a very nice one, too)."
- John Weiland, Intrinsix
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