( DAC 01 Item 29 ) --------------------------------------------- [ 7/31/01 ]
Subject: Monterey, Sequence/Sapphire, Mentor TeraPlace, Saturn/Jupiter
THE WALL FLOWERS: While at DAC I asked Richard Goering, the EE Times EDA
Editor, if he'd ever personally interviewed a chip designer who had done a
tape-out using Monterey's tools. "Funny you should ask that," replied
Richard. "A fews months ago Monterey set up a user tape-out interview, but
they backed out at the last minute. I never heard why."
That little story and this bar chart pretty much tells it all:
Synopsys ########################################### 170 tape-outs
Silicon Perspec. ########### 43
Magma #### 13
Cadence PKS ### 12
Cadence non-PKS ###### 23
Mentor TeraPlace ## 7
Sapphire/Sequence # 6
Monterey 0
Mentor's TeraPlace, Sapphire, and *especially* Monterey are just so far
behind the others, no one takes them seriously. It's especially damning
that Monterey has *zero*, nada, zip -- absolutely NO independently
confirmed customer tape-outs. (Oh, well.)
The other problem is all of these tools are, more-or-less, clones of Avanti's
Saturn gates-to-P&R re-optimizer. They don't do RTL-to-GDSII, and they never
promised to, either. And the problem with gates-to-P&R gates is that it's an
old flow that's pretty much run out of steam. That is, the Apollo/Saturn
flow is very mature and widely used -- and it's the first user benchmark that
the PhysOpt/PKS/Magma salesdroids have to overcome when they're selling their
particular brand of physical synthesis tools. Get at or below 0.18 and you
start seeing Apollo/Saturn falling down miserably 9 times out of 10. And
those fast talking PhysOpt/PKS/Magma salesdroids use this as their personal
invite to start chatting up *their* special 'solution' to Saturn's failure.
"I am still using ApolloII/Saturn and it is working pretty well for us.
We are currently designing in a 0.13 um process and after some pretty
thorough analysis have concluded that most/all of the normal standard
cell libraries suck (Virtual Silicon, Artisan, Nurlogic). They are
generally very good if you want density, but are terrible if you want
any kind of decent performance.
Therefore, we are designing our own library and are getting very good
results. For example, we were able to achieve 200 MHz in 0.25 um using
a structured custom approach to datapath design (which took a lot of
manual work and stayed within the standard cell domain). With this
same block it looks like we are going to be able to reach 400 MHz using
the DC synthesis/Saturn approach -- all you need to converge on timing
is Synopsys and Saturn.
I have heard stories of people that have punted on Saturn because they
couldn't get it to converge. My opinion of this is that they do not
understand how to setup the tech file correctly. We go through an
extensive technology investigation. Part of this is correctly
establishing the technology variables and then making sure that the
Apollo/PrimeTime vs. SPICE timing correlates. Our tech file values
are re-adjusted until this happens."
- [ An Anon Engineer ]
"Magma strengths:
Fixes slew/cap/fanout violations flawlessly. Has separate buffering
commands for trees (>1000 pin nets), long wires, and large capacitance.
Running the same design on Saturn and Magma resulted in 30K slew
violations with Saturn and 6 slew violations with Magma (all 6 were due
to a placement blockage which prevented repeater insertion).
Avanti has no good solution for fixing slew violations due to RC delay
except to run the clock tree synthesis tool on long wires. Saturn does
not address these slew violations.
Avanti does not handle hold time fixing very well. Saturn adds too many
buffers and doesn't always fix every path due to miscorrelation or some
other tool problem."
- from "Been There, Done That" in ESNUG 374 #7
"From my limited perspective, Avanti is losing. They don't have a
real physical synthesis solution, just a tool (Saturn) to do
placement based timing correction."
- [ An Anon Engineer ]
"We did experiment with Avanti Saturn in the old flow; our results were
not that great at that time."
- Bob Prevett of nVidia in ESNUG 346 #5
"Although we called it our "Days of Hell" tape-out, this miserable
process took us 3 months to do. It was like being part of a secret CIA
experiment to test the limits of human sanity. I would run a chip
through Design Compiler and using its conservative WLMs, DC would tell
me it made timing. Then, in the Avanti placement, we'd be 2 to 3 nsec
off on timing. After Avanti Saturn resynth and LSI resizing, the best
we could get was 1 nsec off spec. Go back to try to fix things. We
looped like this forever.
Our fundamental problem was that we were working with three different
timing engines that didn't agree with each other: the Synopsys DC
engine, the Avanti Saturn engine, and our internal LSI engine. Finally,
after 3 months of this we just decided to stop."
- Vijay Angarai of LSI Logic in ESNUG 361 #1
"Yeah... I've seen Saturn in action. Or is that inaction?"
- Leo Butler of Brocade Communications in ESNUG 374 #6
"How about you trade us four of those dolphins for four of these balls?
You guys could really use some balls."
- a Prolific, Inc. floor team member to a Monterey rep on the
subject of DAC giveaways and intestinal fortitude. (Prolific
was giving out sound-effect superballs.)
"John, I am an EDA engineer, focussing on physical design, and a regular
reader of deepchip.com and EEtimes. I have been following the tapeout
debate in detail. I was considering Monterey Design as a potential
job opportunity. I think the people and the technology there are quite
good. But what worried me was the tapeout count (Monterey - 0).
I would greatly appreciate your opinion about the company. I've
followed all publicly available info (Products, Venture funding,
Management, DAC exhibit, etc.) but any inside info and personal
opinion/experience would be invaluable. Thanks for your help."
- [ An Anon EDA Developer ]
"As it looks, Monterey will lose. Magma is still shaky though I wish
them success. I would expect Synopsys, Cadence and Magma; maybe Avanti
to carry on. Maybe only a vendor who is already active in the backend
will survive (then Magma would be out, hmmm ..)?"
- [ An Anon Engineer ]
"Monterey Design sells Dolphin, which accepts a netlist and produces a
layout. Their tool tries to iteratively refine the design to solve
timing, area, clock distribution, signal integrity and power routing
all at the same time. It will do logic optimization as needed. It has
been two years since they announced it and there are still very
few tape-outs."
- John Weiland, Intrinsix
"Magma has an excellent tool! Synopsys has an excellent tool. The
others should be very, very very worried. I've heard nothing from
Monterey, and PKS has no traction since Synopsys DC rules the roost.
TeraForm is another interesting piece of tech, which can be used
*with* Magma/PhysOpt."
- [ An Anon Engineer ]
"Monterey Design Systems: an integrated gates-to-GDSII flow
------------------------ Dolphin, Sonar, IC Wizard (Aristo)
I attended one of their "private suite" demos.
1. Accepts/produces industry standard formats (LEF, DEF, DSPF, ...)
2. Built-in static timing analyzer, capable simultaneous min/max
analysis, and distributed RC analysis, including the effects of
cross-coupling.
3. Timing-driven cell placement with "automatic congestion avoidance";
integrates global routing, clock tree synthesis, power bus routing,
logic re-optimization; supports scan-restitching.
4. Clock tree synthesis is performed concurrently with placement and
a. has fully controllable parameters (insertion delay, skew,
transition time, fanout).
b. supports variable-spacing/width wires w/multiple vias
c. supports multiple clock tree domains and inter-clock skew
constraints, as well as gated clocks.
d. does NOT support "useful skew" concept yet; expected in mid-2002.
5. Shape-based gridless & gridded router
6. Re-optimizes logic: sweeping & constant propagation,
collapse/decompose to choose cells that decrease route
utilization, tech. re-mapping, hold-time fixing, and area recovery.
7. Fully-integrated Parasitic Extraction: 2.5D field solver.
8. For Signal Integrity, includes the following analyses: cross-talk,
electromigration, IR drop.
9. Power Router: chip & megacell power rings, as necessary,
automatically generates std. cell block power mesh, global power
structure can be created from user constraints and edited
interactively; generates via arrays.
Multi-threaded tool supports multi-CPU boxes. Sun only."
- Kris Monsen of Mobilygen Corp.
"* Monterey Design has a handful of unconfirmed tapeouts now, and claim
that their customers (Infineon, ST Micro, & LSI Logic) rave about
them. They also list Broadcom & TI as customers. I like the
IC Wizard-Sonar-Dolphin flow, but we'll have to see how successful
they become. The Sonar tool gives logical designers the ability to
sign-off on a physical prototype with an early & accurate view of
a block's physical implementation, including signal integrity,
IR drop, power straps, clock trees, routing, buffer sizing, and
timing. Dolphin picks up from where Sonar finishes to complete the
detailed physical design in about 6x the Sonar run time."
- [ An Anon Engineer ]
"Monterey
This is another complete physical design tool suite with an emphasis on
early timing closure. The main product is called Dolphin (gates to
GDSII). They also sell Sonar and ICWizard, which are early design
proto-typing tools designed to (you guessed it) provide early timing
closure, better area results, and shorter time to market.
The stated goals of their marketing pitch exactly matched those of
Magma and Get2chip in particular, and to a lesser extent Synopsys.
I guess it makes sense since they are direct competitors with similar
products trying to solve the same problems, but it is very difficult
for a physical design novice to differentiate between their claims."
- [ An Anon Engineer ]
"Sequence Design was formed from Frequency Technology and Sente and then
acquired Sapphire Design. Saphhire sold a tool called FormIt. I knew a
user who said it was crude but he could make it do what he wanted so he
liked it. They have renamed it to Physical Studio and may have added in
some of the Frequency Technology technology to it. You first use the
tool after synthesis and initial placement (like you might get out of
PhysOpt - hint, hint). The tool optimizes netlist and placement for
timing, signal integrity and power (there is obviously only so much it
can do since it hasn't been routed yet). You route the design, then the
tool finishes fixing the timing and signal integrity problems, using a
3D extraction tool for analysis."
- John Weiland, Intrinsix
"Sequence Physical Studio
------------------------
Sequence combined FormIt from their acquisition of Sapphire and with
their former Copernicus product to come up with Physical Studio.
FormIt did timing/SI closure based on global routing results.
Copernicus did timing/SI closure based on detailed routing results.
With the two combined, they have a pre-/post-detailed route
timing/xcap closure solution.
The thing that I think is cool about Physical Studio is it's the ONLY
cross-cap solution that does automatic check-and-repair. Cross-cap
is a crappy add-on in the Cadence/Avanti P&R solutions.
Physical Studio fits into the design flow exactly where the Cadence/NEC
xcap capabilities fit (xcap delay calculation, STA that generates
timing windows, xcap xtraction, noise modeling, gate sizing/buffer
insertion to fix timing and SI problems). While Physical Studio claims
to address SI pre-route, upon closer inspection we find that they are
simply addressing transition time issues on long nets, which virtually
everyone in the industry does anyway. It's a decent tactic, but we
still had thousands of xcap violations on [ Project X ] & [ Project Y ]
after length-based buffer insertion. Just like current solutions, they
largely address timing pre-route. Xcap is really fixed post-route.
The pros/cons of Physical Studio:
- NEC claims to be making very good progress on noise modeling with
Physical Studio. Noise modeling has been one of the most difficult
aspect of xcap handling in both xcap solutions. If Sequence
actually has a well-working noise model (something neither Cadence
nor Avanti had 6 months ago), it might be worth checking out.
- in our Copernicus evaluation, we found you still have to get all the
way out of your P&R tool to get into Physical Studio. That takes
a lot of time.
Some other tidbits:
- OLA is on their roadmap.
- Claim to be...
o Doing hierarchical delay calculation and static timing
analysis now.
o Tuning a noise rejection algorithm (only noise rejection
algorithms I've been seeing are NEC- and Agere-internal).
No one has signed off into manufacturing with Physical Studio yet."
- [ An Anon Engineer ]
"Mentor Graphics
---------------
I didn't have time to meet with anyone from Mentor Graphics nor
evaluate their tools. I did research the following:
1. They have a suite of tools: TeraPlace, TeraOptimize, TeraCTS
- goal is to cover the space between synthesis and detailed
block route
- performs placement optimization
- clock tree synthesis
- placement-based scan-chain reordering
2. They don't have much in the way of ASIC synthesis: they offser
Exemplar's tool (Leonardo) which is targeted mostly at FPGAs/PLDs,
with a push-button interface.
Otherwise, they don't list anything in the way of a standard cell
router. They have analysis/extraction/verification tools."
- Kris Monsen of Mobilygen Corp.
"Mentor has moved their TeraPlace group to FPGAs, to help Exemplar
implement FPGA Physical Synthesis."
- Deepak Sherlekar of In-Chip Systems
|
|
