( DAC 01 Item 26 ) --------------------------------------------- [ 7/31/01 ]
Subject: Quickie Intro To Backend Tools For Frontend Designers
"Quick spectrum of vendors:
Gates Place- Floor- Block Clock Final Extract
ment Planning Routing Tree GDSII DRC/LVS
Synopsys |____PhysOpt____||_CA/FP.Mgr_||__ Route66_(mid-2002)____|
Cadence |____Ambit_PKS__||_____Silicon_Ensemble-PKS_______| |__Assura__|
Avant! |_Jupiter__| |__Planet__| |_ApolloII_| |_Herc_| ...
Monterey |_________________Dolphin___________________________|
Magma |_New__..________________Blast Fusion___________________________|
Get2Chip |_Volare_Topomo_|
Mentor |_TeraPlace_|
General Observations for Physical Design Considerations & Trends:
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1. "Signal Integrity" is everywhere. SI Analysis is emerging as a key
feature in tools now, and we should pay close attention to it in any
flow we use for 0.25um and below. Coupling-capacitance among nets
routed in parallel is an important issue for parasitic extraction, but
also important are "aggressor gates", which are large gates selected
by the logic synthesis step to get fast timing, but which actually
overdrive their output net; a nearby smaller gate whose output net
("victim net") is capacitively coupled could be completely swamped
during the transition, which would dramatically affect timing.
2. IR-drop analysis is just starting to show up in some tools. This is
another area that I think will be important for accurate timing.
3. Timing analysis:
- cross-talk (aggressor/victim nets) is big! (see above)
- mode-dependent voltage
- electromigration
- IR drop
4. New fab tech. rules:
a. Metal slotting
b. End-of-wire metal-overlap for vias & contacts
5. Support for multiple power-wells (e.g., 3.3V for I/O ring, 2.5V for
core); affects timing analysis as well as layout and power buses.
6. All physical design tools still use Sun Solaris as the primary OS,
and many are saying a 64-bit OS is necessary for memory capacity."
- Kris Monsen of Mobilygen Corp.
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