( DAC 01 Item 20 ) --------------------------------------------- [ 7/31/01 ]
Subject: GreenLight, SynaptiCAD
THE NEW KIDS ON THE BLOCK: GreenLight is one of those tiny EDA start-ups
that you 'discover' at DAC if you make an accidental wrong turn on the DAC
exhibit floor. Their product appears to be a testbench generator that's
Perl-based -- which means it's already very user friendly to 98% of the
UNIX using EDA chip designers out there. And SynaptiCAD? Naw, they're not
new. But their tools are inexpensive testbench generators, too.
"GreenLight (Pivot)
We thought this was the most exciting of the new companies that we saw
at DAC, due in no small part to the nice (outrageously expensive and
very tasty) dinner they took us to at Emeril's. This is a small
company (5 people at present) and they are currently profitable. They
swear that if they sold us a passle of licenses, they would be able to
support us. Furthermore, if they had to staff up, they said they would
only hire very good engineers and not foist any losers on us.
GreenLight's product is called Pivot, which they describe as a
"Verification Test Bench Development Tool". It allows you to write a
testbench in Perl. The Perl interpreter (the normal one that everyone
uses) is set up to allow Perl to speak to any simulator without a PLI.
Pivot comes with some packages that allow you to connect to the Verilog
in a number of commonly used situations. You can connect to the
clocks in order to be timing aware in the testbench, thus making a
procedural language work concurrently with a Verilog task.
One "win" in this situation is that you can create tests/testbenches in
Perl, which is a language that most/many designers can use. The more
complex the problem you are trying to solve, the more of a "win" you
get from this approach, since simple monitoring tasks are done just as
easily in Verilog. Furthermore, it enables the design engineer to
begin test without having to wait for verification (assuming the
designer can write Perl).
GreenLight suggests that the recode/retest loop may be executed in a
tighter fashion than if you used C. They also point out that Perl is
better at dynamic allocation than Verilog, and simpler to use for the
same than C.
A strong point of Pivot is the sophisticated randomness that you
can achieve with your tests. The tool provides manually-controlled
weighted randomness, using a variety of techniques, including ranges
and functions for the variables. It also allows you to randomize using
statistical distributions like an inverse gaussian, so you can get a
lot of corner cases and skip the boring common ones. You can probe
the design and evaluate the test, and have the randomness react
dynamically.
Pivot was initially written by these guys when they were contractors.
Their clients kept asking for it to be left behind, so they decided
to make a product of it. The pricing is $15K for the first seat (the
license runs on FlexLM) and less for volume purchases. Maintenance
is about 16% a year and includes full support, all bug fixes, and
upgrades. They will distribute an admittedly small set of examples
as well as a user's guide. They will discuss selling cores of
particular interfaces if there's an interest.
This tool is not suited for use with emulation because it becomes the
bottleneck. They also do not have a goal of automating checkers,
because they don't think there's anything very interesting to be
achieved in this field. They think the checkers that you can automate
are too easy to bother and the harder stuff can't be automated."
- [ An Anon Engineer ]
"As stated before, I'm hoping for Superlog, but you never can tell. We
are not ready to adopt something like that in our group at this time.
There was another "tool" that was put out which tied PERL into the PLI,
rather interesting, it's shareware or something like that, but is
interesting considering our investment in PERL testbenches.
- Dave Brier, Texas Instruments
"I go more with the less expensive tools like VeriloggerPro from
Synapticad as opposed to those that cost 10 times more. While they
may be a little slower they seem to get the job done just as fast
when you consider that you can't always afford to put a copy of the
big boys on everyone's desk. Their working environment is consistent
across all their tools, they reasonably fast (their simulator is at
least as fast as Verilog-XL), and the tools are easy to use. Overall
I think that it's an excellent buy, inexpensive enough to put a copy
on every engineers desk (try that with Synopsys.)"
- Wayne Armbrust, Wayne Scott Associates
"I did manage to stop in at SynaptiCAD, and take at look at their
Testbencher, Verilogger, Waveformer, Datasheet and Timing Designer
tools. These looked very usable and intuitive to operate, supporting
a wide variety of formats and standards."
- Tom Moxon of Moxon Design
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