( DAC 01 Item 15 ) --------------------------------------------- [ 7/31/01 ]
Subject: Superlog, Verilog-2000
EVOLUTION, NOT REVOLUTION: Blurring itself with the much-loved-by-users
Verilog 2000 inprovements, Superlog is grabbing a lot of designer mindshare
when they think next generation simulation. Superlog's biggest strength
is that it's evolutionary -- it's just a superset of Verilog -- so you can
use all your legacy Verilog code on your current project.
"The Superlog language is a good thing."
- Bill Cox of VI ASIC
"Verilog-2000 should quickly be embraced by everybody working with or
processing Verilog. Just by the fact that it supports signed types
makes it much much easier to deal with.
I was suprised to hear so little about Superlog. I personally like
Superlog, but believe that it will not be successful (at least where
I want it to be successful -- above the RTL level) because "it's a
new language" and people fear change."
- [ An Anon Engineer ]
"I'll put my money on SuperLog just because it will cause the least
amount of pain to existing Verilog designers."
- [ An Anon Engineer ]
"Superlog: A C-like extension to Verilog language for higher order
synthesis and verification. Has the systemsim that simulates
Superlog (and existing Verilog). Has systemex that can generate
95 Verilog from a superlog subset (for synthesis).
- Uses no PLI
- Easy to include existing C or Vera.
- Has some C++ stuff incorporated
- Has synth subset defined
- 25-100X speed improvement over Verilog if using the higher-
order constructs.
- Straight Verilog is faster, but hardly anyone uses straight
Verilog. Faster than most Verilog sims that use PLI.
- New verification hooks allow for random stim, transaction
levels, C reference model integration, functional coverage,
temporal expressions, constraints, self checking, multi-
threading, protocol checkers, concurrency, etc.
This was a fast demo. No actual code or seeing the tools run. We had
to leave early."
- Peet James, Qualis Design
"* Although the plethora of C/C++ dialects concerns me, I saw a lot of
progress in this arena. In particular, C-Level has made great
strides since 1 yr ago. Synopsys finally re-licensed SystemC to make
it truly an open standard. From the many talks that I attended, it's
obvious that SuperLog is also gaining a lot of momentum, but I never
had a chance to attend the SuperLog demo."
- [ An Anon Engineer ]
"As you probably know, I am a big fan of Superlog. I think it is the
design language of the future. A major milestone was donating the
Superlog Synthesizable Subset to Accelera from Co-Design Automation.
This means that when Accelera publishes a standard, anybody can write
a syntheis tool for Superlog. If the Superlog synthesizable features
can be added to Verilog, I think I can be a lot more productive
designing. A lot of designers and companies were talking about
Superlog and I think it is happening. One of the ironic things about
Verilog 2001 is that the only Verilog 2001 compatible simulator I know
of is Co-Design's Systemsim!"
- Anders Nordstrom of Nortel
"Another interesting one is the Co-Design's Superlog. They have tools
to compile your Superlog language into synthesizable Verilog. Wonder
the quality of their synthesizable code."
- [ An Anon Engineer ]
"I am impressed with the number of Verilog-2001 features that have
already been implemented in Superlog. I still like the idea of a
superset-Verilog language that permits seamless inclusion of C-models
where appropriate. To me, this makes a lot more sense than forcing
everything into C-models."
- Cliff Cummings of Sunburst Designs
"Looked into Superlog and wish it was open. I worry about converting
over to a closed language. The Verilog extensions could beccome habit
forming if I started to use them. Next I want Design Compiler to
support them directly w/o going through Co-design's conversion tools.
I am going to stick with Verilog-2000 for now.
- Phil Kuglin, Credence Systems Corp.
"I wonder how Superlog will do with VCS's new DirectC interface."
- [ An Anon Engineer ]
"I have a feeling that Superlog is kind of next step to Verilog, but am
yet to see any good design being done with it. So for the moment I
would stick to VHDL/Verilog."
- [ An Anon Engineer ]
"The interesting thing about C++ as a design language (SystemC, CynApps,
etc.) is that while some companies were promoting and have some tools
available for it, it didn't seem to be gaining any real momentum.
It will be a while before it becomes mainstream because of the many
disadvantages that it has.
Superlog is gaining many adherents; it is a superset of Verilog; it
isn't standardized yet, but eventually it could be a good alternative
to Verilog (adds more capabilities) and C++ (it's still Verilog-like).
Co-Design Automation controls it now, but there is a standardization
committee appointed."
- Henry So of Mobilygen, Inc.
"I don't think C is going to overtake Verilog anytime soon, especially
with Superlog on the way."
- [ An Anon Engineer ]
"Verilog 2000:
Haven't used it yet. From what I've read of it, it's better than the
old Verilog but still a lesser language than VHDL. VHDL has more
functionality than Verilog 2000, it is less cryptic, has better code
checking (no need for a lint tool) and it's already supported by loads
of tools. So why people simply don't switch to VHDL? Must be a North
American (US & Canada) thing since they like to do things the low
quality and unlogical way (Verilog vs VHDL, T1 vs E1, imperial vs
metric, gas slurping SUV engines vs fuel efficient diesel engines,
wooden houses vs stone/brick/concrete houses, the voting system, etc.)
Anyway, I'm getting side tracked here."
- Menno Spijker, Mitel Semiconductor
"Verilog 2000, once it gets supported by all the tools, will be a nice
improvement."
- Oren Rubinstein of Nvidia
"There is always the question of which is faster NC Verilog versus
VCS. I have never testbenched VCS so I can't answer from experience.
When I asked around at the last SNUG people reported that it depended
on the design. On the other hand, Cadence is certainly dragging their
feet about implementing the Verilog 2000 features. That alone may
prompt us to eval VCS."
- Kristie Armentrout of Tektronix
"Verilog 2001 will be great if vendors support it. At last we will
have built-in file reading operations. Superlog sounds intersting,
but I haven't seen it yet."
- Andrew MacCormack, Tality/Cadence
"We are excited about Verilog 2000 as soon as it is fully adopted. We
can not afford to use two different versions of Verilogs for simulation
or synthesis. Lint tools are great, too. CoverMeter gets some use
here. I think that NC Verilog is increasing in use at Scientific
Atlanta although VCS remains king."
- Tom Coonan, Scientific Atlanta
"CoDesign Automation: Home of Superlog & the SystemSim simulator.
Superlog is a superset of Verilog that also borrows from C & C++. Some
of the features include structures, types, interfaces, processes, and
state machine syntax. It is intended for use from the architectural
level down to gates.
There is a synthesizable subset of Superlog that may be compiled in
Synopsys if you get the SYSTEMX tool from CoDesign, or you may also
synthesize directly in Get2Chip's tools. However, there is no way to
formally check Superlog versus the created gate level netlist.
Superlog offers timing control because Superlog and Verilog functions
may call each other recursively, and therefore Superlog can call a
Verilog function that watches timing events.
SystemSim is the CoDesign Superlog simulator. The Superlog/SystemSim
combo eliminates the need for cosimulation in system level sims,
because the hardware and software is all written and simulated in C.
You can still use the PLI, or a similar software tool called Cblend
that they provide. (Cblend is the interface between Superlog and C,
C++. It allows you to compile C to a shared object and call it from
the simulation.) The whole simulation runs faster in part because
there are some compile optimizations that you normally need to turn
off when compiling a PLI and Verilog simulator, that you may leave
turned on when you use Superlog.
Features include:
- The ability to abstract architectural concepts like interfaces and
then use the abstractions to define specific implementations (like
defining packets on an interface);
- The use of dynamic processes like a fork without a join (useful for
things like protocol checkers and other temporal checking);
- Feedback into tests to adjust the randomization according to how
the test is developing;
- Claim of 2-4x improvement in speed over Verilog/PLI simulations.
The downside, as with all these high-level abstractions, is that in
real life, you never do a whole chip using fresh RTL (except at SGI)
so you run into the cosimulation performance problem anyway."
- [ An Anon Engineer ]
"I am eagerly awaiting Verilog-2000 compliant tools. While DC handles
it, VCS doesn't, so it is useless to me for now. Just the 'generate'
statement alone would remove hundreds of lines of typo-prone code
from my test benches."
- Jeff Deutch, Avici Systems
"I'm considering Superlog as hopeful, simply for the same reason that
Verilog has been around and isn't going away. At least I'm only
extending a language, not having to learn yet another language."
- Dave Brier, Texas Instruments
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