( DAC 01 Item 12 ) --------------------------------------------- [ 7/31/01 ]
Subject: Debussy, @HDL, Veritools, EDAptive, iMODL, Diagonal
HAPPY, HAPPY, JOY, JOY: People just luuuv Debussy. I'm not saying that
sarcastically. They really do! I had to do quite a bit of searching just
to find these 3 almost negative comments about Novas Debussy. Other than
these 3 comments, I was flooded with "Debussy's great!" comments. Easily
I could have cut & pasted at least 50 pro-Debussy user comments here.
And despite the Debussy hysteria, it looks like the newbie @HDL is jumping
in with their own waveform viewer to challange Debussy! Initial impressions
are that @HDL could steal a chunk of Debussy's market, but how much share
no one knows. It'll be good to see competition come back in this EDA niche.
"Debussy is good if you are using gates or a complex hierarchy, but
without it's cell library (which depends on your foundry) Debussy is
useless. Since most people do formal verification these days the need
for this tool has gone down."
- [ Kenny, from South Park ]
"Novas Debussy
Strengths
- Very interactive. Crossprobes to RTL source.
- Schematic view feature is intuitive and useful.
Weaknesses
- QA, testing and documentation are pretty poor. There were 17 beta
releases of v5.0!
- Compression can be inferior to SignalScan.
- We have benchmarked Debussy as neither freeing shared-memory
allocation nor even checking memory is available before blindly
malloc'ing (during decompress after the .fsdb file is loaded and
when signals are selected to view).
- On large databases Debussy simply falls over when it has grabbed
all usable memory. The R&D took 2 months of my time to prove this
occurred, then have been arguing with me ever since that this does
not constitute a "realistic use case".
- Confusing and inconsistent use in waveview of color and hatching
between edges, single and bussed nets.
If Novas would fix these problems then they would have a pretty viable
solution."
- [ An Anon Engineer ]
"When it comes to debug environments, I am sold on Nova's Debussy.
I recently took the training and started using it. It is so easy
to use that even a manager can use it. :-)"
- Anders Nordstrom of Nortel
"The Veritools booth was right next to the Novas booth and there was
a poster in the Veritools booth pointed at the Novas booth touting
that Veritools could do source code debugging for 1/4 the cost of
the Novas competition."
- Cliff Cummings of Sunburst Designs
"@HDL looked pretty good for their Waveform system. They might give
Debussy a run for their money. Their clock domain checking stuff
looked pretty good also. No one talks about this, but everyone has
either had problems with cross clock domain signals and figured out
a scheme for fixing them, or they don't tape out working silicon."
- John Szetela of AMD
"Two waveform viewers I saw at DAC that got my attention were the
Novas Debussy and @HDL waveform viewers. Debussy has active source
annotation and so does @HDL -- which I find very useful when debugging
RTL. In Debussy, you can see the value of each signal right underneath
the variable name in the source code window, and as you move around in
time the value reflects your current position in time. @HDL shows a
control flow view instead of having the signal values under the
variables in thee source code which is not quite as good but adequate.
@HDL waveform viewer also now claims to have a scheme to support
internal Vera variables, as opposed to just the global Vera variables,
which is a big help in the debug of testbenches. You can see what the
testbench is actually putting out on to the RTL. Have not seen it yet.
@HDL was claiming support for pipeline viewing but haven't seen that
yet. They also support automatic memory inference which allows you to
look at the memory contents directly rather than tracing the values in
the waveforms.
One complaint I have on Debussy is it does not highlight the waveform
even when the signal is selected. Frequently I found my self looking
at the wrong waveform (one above or below it). They also do not have
Vera integration. If @HDL's Vera integration works as advertised then
it will be a big plus for them."
- Faisal Haque, Cisco Systems
"We own and use DeBussy and like it over the old SignalScan Pro tool
Cadence has."
- Phil Kuglin, Credence Systems Corp.
"Novas DeBussy is an amazingly nice debugging environment with a great
user interface."
- Kristie Armentrout of Tektronix
"Heard from other's in our company that they keep finding out neat
features in Novas Debussy by attending demos they give and DAC was no
different. Will be having them in to go into some more details on some
of those features (don't have the details). Also, SureLint's race
detection feature is pretty helpful as well."
- Scott Evans of Sonics, Inc.
"Novas DeBussy is very popular here and easy use."
- Jeong-Fa Sheu of Acute Communications
"I love Debussy and have demo'd it and tried to promote it here and at
my last company. I think it has the most payback when you are forced
to debug or do verification on designs with which you are not familiar,
like purchased IP or designs passed on from others. It has less
payback when you are already familiar with the design, then it is just
a fancier waveform viewer and code browser. The problem I have had
with it is that to get the most out of it, you have to use it a lot.
If you have limited licenses, it is hard to share. It requires a real
buy-in by a whole group and that has been hard to sell to mgmt."
- Tom Loftus, Intrinsix
"Novas DeBussy has become an important debug tool for us; we couldn't
get along without it anymore."
- John Lynch of Pixelworks
"Debussy is our favorite debugger/waveform viewer. This is not even
their main tool but they have the best schematic viewer in the
industry. We are fortunate to have excellent support from Novas."
- Luis Basto, Analog Devices
"EDAptive Computing sells a tool that accepts requirements in "Rosetta"
and generates tests automatically. They claim that their language
models requirements better than Verisity's e language.
@HDL sells a tool that creates test benches based on both built-in and
user programmed assertions. It can also do directed random testing to
cover FSM arcs (compare this to 0-in, which tries to cover all
COMBINATIONS of arcs for every PAIR of state machines).
Diagonal Systems' Bestbench tool generates testbenches from graphical
entries of timing, etc. It is now transaction based, so you don't have
to describe everything on a clock by clock basis.
Testbencher Pro from Synapticad is a graphical testbench generator. You
define bus functional models and transactions and it makes a wrapper.
You then insert the function in the wrapper. It can also read data
files automatically. It outputs to VHDL, Vera, System C and Vera.
Verisity's e language is on the way.
Beach Solutions' tool takes an address map to your SOC and some
comments describing it, and it generates documentation for your
software folks, some C code for testing the part, and it creates
your low level functions like drivers. This year it generates Verilog,
VHDL and C BFMs and test benches to test all bus interfaces.
iMODL was bought by TransEDA. They sell bus functional models of
Intel and MIPS processors and of PCI interfaces."
- John Weiland, Intrinsix
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