( DAC 01 Item 11 ) --------------------------------------------- [ 7/31/01 ]
Subject: Foresight, Vast, Coverify, TOPS, Cynergy, Cardtools, Axys, Beach
THE CROWDED FIELD: In terms of Darwinian evolution, we're seeing an
explosion of lots of little new EDA companies hoping & praying to ride a
much wanted wave of C-based design methodologies. The truth is going to be
a bit more harsher than they'll want with the economy tanking and the strong
dislike of C-based tools most HW designers have. The only safe haven these
tiny C hopefuls have is in the Sea of Verification Tools -- but that
ecology can only support just so many companies, so expect to see some wide
spread die offs coming soon for many of these tiny C companies.
"AXYS Design Automation
----------------------
AXYS Design Automation offers MaxSim, a C/C++ based environment for
cycle-accurate synchronous multicore SoC simulation.
The intention is for SOC architects to create models, or virtual
prototypes, of their designs early in the pre-silicon phase to verify
and integrate embedded software applications before tape-out.
ARM is working with AXYS to make their processor models part of
AXYS's library."
- Carina Chiang of Agilent
"1.1 C Tools
Foresight Systems (foresight-systems.com) has a high level tool
designed to be an executable spec. You enter your system function
as a hierarchical block diagram with C code behind the blocks, and
initially it's not even clear which blocks will be hardware and which
software. You do hardware/software partitioning and trade-offs within
the tool. Then co-simulate with other simulators, such as Modelsim,
Visual C++ and Matlab and interfaces to the DOORS requirement tool.
HyPerformix sells a tool to do performance modelling of different
architectures, based on a graphical description of the architecture.
Vast Systems Technology sells a hardware/software co-development tool
that's like Mentor's Seamless but has and embedded development system
and can do architecture trade-offs. Your architecture can be described
in Verilog, VHDL, C or Matlab.
Coverify Solutions sells a hardware/software co-development tool that
accepts Verilog RTL and C code and a compiler. It doesn't actually
simulate, it hooks into the PLI of your simulator.
Derivation Systems, Inc. sells a tool that uses a formal verification
method called derivation. For normal formal verification, you code up
your RTL, then you create a second description of your design and
compare the two. In this tool, you enter the desired function in a
LISP-like language, then partition it to lower and lower levels until
you reach RTL (or even gates for Xilinx or Actel). The act of
partitioning is controlled by the tool in such a way that the lower
levels are guaranteed to be equivalent to the original description.
Cynergy sells a tool to graphically capture your event flow, then you
represent your datapath functions either as a graph or as C. It
outputs cycle accurate C and Verilog RTL. They have another tool to
build a system out of C models, which inserts hooks to a debug
environment with waveform viewing, etc. They have another tool that
translates Verilog to C, so if you've got a pre-existing design, IP,
etc. you can put it in your all C flow.
TOPS Systems also sells translators from both VHDL and Verilog to C.
CoWare makes tools for C based system design. They can accept C
(SystemC or Coware C) or synthesizeable VHDL or Verilog, and can
translate to RTL, simulate it, and also synthesize interface logic
(sounds a little like YXI).
Poseiden sells a tool for processor architecture exploration. You
represent your processor using their language and it automatically
creates a compiler for it and a simulation model.
C-level sells a tool that accepts C and outputs RTL. The particular
subset of C that they now like is called "cycle C". They claim their
tool is faster than competitors because it's plain old C, not C++.
They are adding debugging, waveform viewing and support for multiple
clocks.
Cynapps and Chronology merged to form Forte Design Systems. They have
a C++ to RTL tool and they're one of the established players in the
market.
Future Design Automation sells a tool that goes from C to VHDL or
Verilog. They can use cycleC like C-Level, but they can also use
higher level C (algorithmic or I/O accurate). They synthesize the
architecture separately from the interface (to busses, etc.).
Celoxica has a cycle accurate C simulator and can synthesize directly
from HandelC to FPGAs. They currently support Xilinx and Altera. Actel
and Atmel are coming.
Axys sells a C model simulator that is transaction based, a library of
C models for common cores (like MIPS, ARM7, ARM9 and OAK) and also a
tool that creates C models for your own processor if you describe it
in their language.
Cardtools sells a tool to do C-based simulation of various processors
and RTOS's (they have libraries of both) to help you pick the best ones
and do behavioral simulation of your system.
Endeavor Intertech Corp. sells a tool that allows you to simulate cores
in C++ with your embedded code. They have some models they can provide,
and allow you to mix model types (C or C++, don't know if it takes all
flavors).
ML Designs sells system level design tools for doing performance
modeling, behavioral modeling, and RTL.
Williamette, which is known for HDL training, now sells a SystemC
linter.
Beach Solutions' tool takes an address map to your SOC and some
comments describing it, and it generates documentation for your
software folks, some C code for testing the part, and it creates
your low level functions like drivers. This year it generates
Verilog, VHDL and C BFMs and test benches to test all bus
interfaces."
- John Weiland, Intrinsix
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