( DAC 01 Item 10 ) --------------------------------------------- [ 7/31/01 ]
Subject: Mentor 'Platform Express', Seamless, Synopsys Eagle-i, Summit VCPU
SOMETHING OLD, SOMETHING NEW: Mentor has just taken 100% ownership of the
old fashioned C world of HW/SW co-design. Synopsys just stopped selling its
failed Eagle-i product, few seem to know anything current about Summit's
(Innoveda's) VCPU, which means that Mentor's Seamless rules the roost here.
And, to boot, Mentor's announcing "Platform Express" -- the next logic step
up from Seamless. Mentor's simply kicking ass here in this niche!
"Mentor Seamless is far ahead of Eagle and VCPU. Mentor is the leader."
- Sean Smith, Cisco Systems
"We were informed, shortly after purchasing the tool, that Eagle-I is no
longer being offered to new customers. Nor are new processor models
being developed, although Synopsys claims that current customers will
be supported.
The product appears to be well on it's way to end-of-life. We also
have issues with Mentor/Seamless (which we do not own), in that models
for certain DSP processors we require are not cycle-accurate, whereas
such models are available for Eagle-I. My other comment would be that
performance is limited at best, at least with the simulators and
workstations we now own. In our case, this is primarily to support
the software engineers. We are migrating toward use of FPGA prototypes
and development boards, which are significantly faster for this
purpose. However, we may consider Endeavor Intertechs's CoOperate
models as an alternative."
- [ An Anon Engineer ]
"We have just started using Seamless. I think that we will use it in
the old fashioned way (i.e. HW/SW coverification). We use C models
but outside of our HDL environment at this point."
- [ An Anon Engineer ]
"I have evaluated Seamless and Eaglei and used what was Summit's VCPU
tool. These tools can be valuable in situations where software is an
integral part of the design and necessary during verification. They
will continue to be somewhat handicapped by their slow speed but can
be a useful substitute for a full blown hardware based solution like
Quickturn."
- Tom Loftus, Intrinsix
"Mentor Graphic's New "Platform Express" Tool
--------------------------------------------
Mentor Graphics platform-based tool (to be announced August 13, 2001),
uses platform-based design to help designers create processor-based
design, with peripheral IP for the purpose of trying out architecture,
running diagnostics, and running firmware. EE Times tentatively
called Mentor's tool "Platform Express", so we'll use that name here.
This class of tools is a wake-up call for ASIC designers.
Platform Express implies that the value of the system exists in
firmware rather than in the hardware. With platform-based design, the
designer can capture an SoC design idea by selecting the platform core
and IP blocks from an XML catalog of parts.
Verification of the hardware and software can be performed using a
hardware/software co-verification environment, such as Mentor's
Seamless CVE. (Okay, so there might be a performance issue here.)
Based on the results, the designer can make changes to the design,
and re-verify the results.
Like any hardware/software co-verification tool, Mentor's Seamless
is limited by the performance of the event-driven simulator such as
Mentor's ModelSim, on the RTL, so Mentor suggests using an emulator
in place of the simulator.
Customers of processor providers will get free access to Platform
Express. But they will need to buy or own licenses for Mentor's
Seamless CVE, XRAY debugger, ModelSim, and possibly an emulator.
Each IP block needs an XML representation, so that the block can be
part of a catalog of parts in Platform Express. If you alter an IP
block, you must change the XML, if you change the pinouts or registers.
In the future, if you create a custom IP block, you must create an XML
representation for the IP block."
- Carina Chiang of Agilent
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