( DAC 01 Item 9 ) ---------------------------------------------- [ 7/31/01 ]
Subject: Cadence Testbuilder/Cockpits, Celoxica, Avery, FTL, Denali, Provis
AN ALTERNATE UNIVERSE: OK, so HW designers absolutely HATE C, and Synopsys
is getting all sorts of grief for its much maligned SystemC 'initiative'.
But, in the verification world, Cadence appears to be wooing its customers
with it's Testbuilder C++ code. People were just gushing enthusiam for it
and saying things like "with Testbuilder C++, I don't need to bother with
Vera, Specman, or Rave!" People also *loved* the idea of being able to
interface to both Synopsys *and* Cadence simulators *without* being locked
into anything proprietary. The other neat thing about Testbuilder is that
is supposedly lets you even mix Verilog and VHDL sims, too. Whoa.
Avery Design Systems is doing something similar to Cadence's Verification
Cockpit and the customers who have written about Avery seem to like it.
On the Yet-Another-Flavor-Of-C front, Celoxia was pushing its version of C
(called "Handel-C") at DAC for their C-to-FPGA synthesis tool. Good luck.
"Cadence: Testbuilder. Chris and I lucked out. We wanted to
get the scoop on Testbuilder, but oddly Cadence had no
real demo (in suite or on floor). We signed up to the closest
thing, and we were the only one, so it ended up being a
impromptu Testbuilder demo/Q&A. The Testbuilder suite is a
free, open-sourced C++ code, and takes a mini class to
really understand (I would agree with this, as both Chris and I
did not get a very full sense of the actual Testbuilder code
and how it works all together).
Things we saw that were cool:
-doxygen is a free tool: (like graph in e) that auto documents
(via HTML output) your C++ code. It makes UML-type diagrams
(much cleaner than graph), and hyperlinks to all the code objects
-Overall the C code looks a bit more cumbersome to write and
read.
-Has temporal expressions: First glance looks like it can do
most of what the other HVLs can do.
-Coverage: It is more integrated with debug. You can chase data
thru Signalscan. You can modify testcase code on the fly,
rerun, and see the coverage and Signalscan update on the fly.
-Integration with Signalscan is very good. Can see all the C++
constructs in various modes. Everything is color coded and
links together.
Need further investigation to understand the actual Testbuilder
code (free part) and the tool part (not free).
- Peet James, Qualis Design
"Verification "Cockpits" are a non-starter for me. Adding another
GUI layer of abstraction on top of my tools has no payback for me
and merely makes debugging of tool problems harder because the
mapping from the GUI to the underlying tool is never well documented.
I prefer batch mode operation controlled by scripts. Mouse clicks
are always hard to document."
- Tom Loftus, Intrinsix
"The Cadence OpenSource TestBuilder C++ library looks like it has
potential as an alternative to Specman and Vera. It lets you do
testbench development in C++ and is supposed to work with all the
Cadence simulators (and even VCS). For people who already use these
simulators, TestBuilder will allow them to move towards the C++ realm
and explore what it has to offer for verification without being locked
down to a proprietary language."
- [ An Anon Engineer ]
"We are in the early stages of our first project using Testbuilder
(Cadence). At a glance, I can see there is some potential for writing
more powerful testbenches using C/C++. But, in the same breath, I note
that it is yet another language for developers to master, which may
dilute the user's knowledge base, by requiring broader and less
specialized knowledge of multiple languages. One must stay ahead of
the curve in order to stay employed, yes?"
- Mike Bly of World Wide Packets
"You forgot to ask one question in this category. What about
Verification Cockpit by Cadence? We do not plan to use or look at
Vera, or Specman, or Rave. I personally attended Vera training more
than 2 or 3 times, and I do not remember a single thing. In my case
I never got to use it. However Cadence's TestBuilder uses C++ TVMs.
C++ language for Verification using TVMs makes sense, and would be
less expensive compared to Specman or Vera."
- [ An Anon Engineer ]
"I thought Cadence TestBuilder was interesting but my impression from
talking to them is that it is still very raw. I have not downloaded
it, but I intend to for cost reasons. The most interesting feature was
its interface to Cadence's SignalScan product. It seems that you could
use this to create a database of both environment events and DUT events
and do searches using Tcl scripts to obtain functional coverage info.
Functional coverage in Specman works great until you need to cross a
few hundred points (which we do).
Also, we have used Denali memory models for the last two projects.
First, a chip with a DRAM controller designed by a college hire and
second, a design with 3 different Rambus controllers. (Need I say
more?) Both chips came back without flaws in those controllers."
- [ An Anon Engineer ]
"Had Celoxica in for a demo and was impressed with their tool which is
more of a C code to FPGA synthesis flow. In general, C oriented EDA
tools don't seem like an improvement. I see enough problems with
turning "C programers" loose with C++ and RTOSs. C oriented EDA tools
just make sloppy habits more difficult to deal with."
- Rick Price of Ensemble
"I looked at Celoxica. Their philosophy seems to be to abstract hardware
engineers out of existence. Nonetheless, an interesting approach;
could be useful for rapid prototyping of new technologies."
- [ An Anon Engineer ]
"Celoxica, the "Handel-C" people: They are working on a new tool that
will automatically convert from ANSI-C to Handel-C, ready in a couple
of years. But hang on, I thought that the idea of coding in Handel-C
was that a "software engineer" could write it. Now you're telling me
that it's sufficiently different from "real" C that we need a converter
that takes two years to write?! This doesn't really suprise me: all
the Handel-C code I've ever seen could be trivially translated to VHDL
or Verilog line by line, and is far from how the same problem would be
coded in "real" C. This stuff is complete and utter junk."
- [ An Anon Engineer ]
"Provis sells their ZOIX Verilog simulator, which allows you to split up
your simulation between a large number of workstations, where the
partitioning is done based on modules. One of the guys in my group is
evaluating it; he thinks it's not quite ready for prime time but it's
getting there fast.
Avery Design Systems sells a Verilog simulator that also allows you to
run your simulation on multiple nodes like Provis's ZOIX. They also say
they have a linter, code coverage tool, protocol checker, and have
hooks for easy random testing. It sounds a lot like Cadence's
Verification Cockpit (as of last year Cadence's code coverage sucked,
though).
FTL Systems sells a simulator that takes VHDL, Verilog, the analog
extensions to both those languages, and SPICE. They have no plans for
C/C++ in the near future. They also can simulate on multiple nodes like
Provis. The digital <-> analog interface is defined using AMS specs.
Electronics Workbench sells a tool that can mix VHDL, Verilog and SPICE
(no analog HDL extensions?). The digital <-> analog interface is done
via a GUI. They do mostly boards or small ASICs."
- John Weiland, Intrinsix
"Being from a Cadence-house, I'd say NC-Verilog is solid, but I'm
concerned about their (Cadence's) GUI. Pretty primitive to the point
where I still prefer the command line. And... being a user of
Signalscan, I fear it (Signalscan) may be a tool going the way of the
dodo as Cadence assimilate's it. Too bad they are putting a lot of
weight into what their SimVision users are saying about Signalscan
as they perform this assimilation. They are ruining a solid tool."
- Mike Bly of World Wide Packets
"Last year I looked at Synopsys CoCentric and TransModeling tools. I
have yet to see the "magic bullet" that will solve all of our design
problems. We have an internal co-simulation environment that would
present some integration issues. Also, our IP is in the form of RTL
(both VHDL and Verilog) and we would like to keep it that way. I am
more interested in the extended RTL approach - both Co-Design's
Superlog tools, and Avery's Verilog-C Kernel apparently can bypass the
PLI interface for efficiency, and provide other facilities as well."
- [ An Anon Engineer ]
"One of the technologies that grabbed my attention while roaming the DAC
floor was from Avery Design. Avery is trying to address verification
speed, capacity and modeling flexibility. Especially on the modeling
side, what they have was interesting: they have integrated protocol
checking constructs, testbench automation via C/C++ etc into VCK, their
Verilog simulator. The good thing is that I can mostly live within
the Verilog confines for my modeling & testbench automation."
- Nagendra Cherukupalli, Cypress Semiconductor
"I really liked what Avery Design was showing. They say they can speed
up my VCS simulations by 5+ times using multiple VCS simulations
running in parallel. This is important for us for verifying VOIP and
MPEG4 designs running on our configurable Jazz processors. I also like
their Verilog and C/C++ based testbench automation. It has the same
features as Vera or Verisity, but it's based on Verilog and C. The
only negative is I do not want to co-simulate VCS with their Verilog
simulator. Unless there is an advantage I do not want to be forced
into having to use new languages or simulators. They should make it
run directly with VCS. Overall I was impressed, though."
- Jeff Lillie, Improv Systems
"IP Vendors (Denali)
- Providing DDR-SDRAM Controller
- Silicon-validated
- started development 2000
- validated on user's ASIC
- configurable using Web-based GUI (DataBahn)
- # of address/data bits
- address mapping
- timing parameters
other options (ECC, Scan, low-power mode, self-refresh etc.)"
- [ An Anon Engineer ]
"Denali Software:
Presentation and Demo on the Pureview post processing function that
Denali is adding to their tool suite. In the past Pureview (aka their
memory debugger) could only be used with the simulator interactively
and it limited some of its usefulness. Starting with release 3.0 this
function will be available in post processing mode.
You can use their debugger to see the history of a given location in
memory and a bunch of other features. More interesting than this is
the integration to Debussy that they are jointly doing with Novas.
You will be able to launch Pureview from Debussy and when tracing in
Debussy and if you come across a Denali model the trace function
in Debussy will trigger the trace function in Pureview and synchronize
the time and the instance. This should be provide a seamless hand off
when crossing domains between Debussy and Denali and give the debugger
more flexibility to trace problems between DUT and memory. I specified
the initial function for this and drove both parties to pursue this and
am very happy with their cooperation and the results. Look for this in
Memory Modeler v3.0 and this will work with any version of Debussy.
Denali also has some slick web configuragble memory controllers they've
branded as Databahn. Better set of features than what I have seen in
other IP and knowing its from Denali tells me it will work."
- Sean Smith of Cisco Systems
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