( DAC 01 Item 7 ) ---------------------------------------------- [ 7/31/01 ]
Subject: The Chip Designer's Intense Hatred Of C/C++ HW Design
A UNIVERSAL HATE: Three months ago, I got a barrel full of C/C++ hate mail
when I did the SNUG'01 Trip Report. (SNUG'01 #14) Not much has changed
since then except I have a crop of different names this time saying the same
message in unison: "C SUCKS AS A HW DESIGN LANGUAGE"!
"I think there is only one thing keeping SystemC alive ... Ron Collett
has not yet declared that SystemC is the language of the future! ;-)"
- Cliff Cummings of Sunburst Designs [ A few years ago, Ron
Collett declared that VHDL was the language of the future. ]
"If we do anything it'll be Superlog-based in the simulation arena."
- Mike Carter of Mosaid Technologies
"Who cares about C? Give me Matlab and VHDL any day."
- [ An Anon Engineer ]
"So far, I'm not a fan of a "C" type language for hardware description.
It may have a place in testbenches and verification depending on how
difficult the interface to Verilog is.
- Kristie Armentrout of Tektronix
"I personally think all this C synthesis stuff is a fad. It'll never
go anywhere, or at least we will never use it until you can read C
directly into Ambit or Design Compiler. We don't want another
translation level to have to debug through when things go wrong."
- Duncan Halstead, LSI Logic
"The entire C arena is still way to fragmented. Too many vendors are
pushing their flavor of C. I don't think we will be doing design in
C any time soon, if ever. HDL's were created for a reason."
- Anders Nordstrom of Nortel
"We didn't look at these C tools. What's the matter with Verilog?"
- Richard Lowry of Starburst Technologies
"C is yet another time sink. We looked into SystemC and C-Level some
time ago. I see 2 places where it may be of some use: 1) *very* large
designs where standard RTL is too slow and 2) true system level
modeling where our system SW is integrated. Our designs are not large
enough to warrent this and our software department simply uses a memory
map model to verify their behavior. True up front system modeling
where real trade-offs are done can be done in standard C/C++. What I
saw was once you followed the restrictions these compilers required why
not simply use HDL?"
- Phil Kuglin, Credence Systems Corp.
"Quite frankly, if you think you need C to describe you're hardware you
shouldn't be designing hardware! The idea of software engineers trying
to create hardware scares the %&$@ out of me."
- [ An Anon Engineer ]
"What problem is C trying to solve?"
- Oren Rubinstein of Nvidia
"We use C/C++ for software and VHDL/Verilog for chip design. Enough
said."
- Carl Wakeland, Creative Advanced Technology Center
"I've been watching this from the outside for a long time... watching
the debate between C, Superlog, Verilog, VHDL, etc... Every time I
look at code for a design generated in some language other than Verilog
or VHDL, I look at it, and my eyes glaze over. And I think to myself,
why would anyone want to subject themselves to this???"
- Gzim Derti, Improv Systems
"I prefer to prototype my algorithms in C, then write the Verilog
code. I love the idea of verifying functionality with FPGAs. I
would compare the results to the original C code output."
- Bill Cox of VI ASIC
"C is a HW solution looking for a problem.
The software folks spent years thrashing through various languages and
going in and out of assembler until C came along. C allowed both
low-level bit twiddling and higher-level programming, and rapidly
became the standard. C++ is making inroads, but C is still where
the bulk of the code is.
Verilog is our C. It spans the gap nicely between bit twiddling and
higher-level design. Designers love it. C twisted into hardware will
never be as good as Verilog is for doing hardware design. You might
tolerate it to get one of 2 things - free simulators and software
compatiblity.
But will the simulators really be free? And, given that many of us
already have lots of Verilog licenses, is this compelling? Give me
an example of the EDA community switching to an inferior tool because
it's cheaper. Sure, a few people will go for it, but the bulk of the
EDA community is focused on time-to-market and productivity, and a
few 100 k dollars in sumulation software is just not that important.
And I think software compatibility is over-rated. The tools exist
today, and few people use them. This idea of feeding your PDF spec
into some tool and out pops a system is silly. All the partitioning
tradeoffs are where the engineering contribution IS.
So, what's the next step? More Verilog, with something like Verilog++
(Superlog) creeping in."
- Paul Zimmer of Cisco Systems
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