( DAC 01 Item 5 ) ---------------------------------------------- [ 7/31/01 ]
Subject: InTime, Icinergy
A MAN WITH A PLAN: Chip-sizers or chip-planners are the best way to explain
what InTime and Icinergy do. Their tools don't lint RTL code nor do they
do any form of synthesis -- they're more like *estimation* floorplanners
with a little bit of power/ground planning thrown in. The emphasis is on
quick & dirty *estimating*, not actual final production. These tools are
controversial because designers are used to just doing estimates by hand.
"InTime Software's Design Arena
------------------------------
Design Arena is a chip-sizer, which can be run before any RTL is
available. Design Arena creates a top-level chip floorplan. It
creates an I/O frame, calculates the number of power and ground pads,
and generates power and ground topology for all the different regions.
It then passes this info to InTime's Design Warrior, providing a
starting point for Design Warrior's floorplan.
Design Arena appears to be an entry point into Design Warrior rather
than a standalone tool."
- Carina Chiang of Agilent
"Icinergy's SOCarchitect and InTime DesignArena are similar in that they
both use library and process data to refine the physical floorplan and
parasitics even before the RTl is completed. You can graphically edit
blocks to create instances and wiring, and then export RTL templates,
or import RTL, or just enter gate counts. You know, the stuff that
most of us run Excel spreadsheets to generate design planning
estimates. The InTime DesignArena tool is designed to be web based, so
that large companies, foundary houses, and design houses could deploy
it for customer use, design planning and quotations.
Both Tera System's "TeraForm" and InTime Software's "DesignWarrior"
display logical and physical heirarchy views of your RTL, and provide
floorplanning and parasitics "under the hood". They also provide
partitioning guidance and generate back-end constraints to drive
gate-level synthesis and layout. These are promising new tools that
look to achieve early design closure."
- Tom Moxon of Moxon Design
"Icinergy's SOCarchitect
-----------------------
Icinergy's SOCarchitect is a pre-RTL floorplanning tool that focuses
on early capture of the physical architecture, before the RTL is coded.
SOCarchitect provides preliminary info on die size, block sizes,
congestion, timing, and power - all this before synthesis is performed,
and even before RTL is available.
Before RTL is available, SOCarchitect can estimate the size of a chip
and what the interconnects will be, at an architectural level. It uses
a symbolic router to do a quick route to derive the interconnect delay.
As RTL becomes available, the user can refine SOCarchitect's estimates.
If RTL is supplied, SOCarchitect makes "set loads" to Design Compiler,
PDEF files for PhysOpt for physical hierarchy and port locations, macro
definitions in LEF, and component instantiations in DEF.
The inputs to SOCarchitect (prior to RTL) are:
- LEF for existing IP blocks such as memory, hard IP
- Block estimates: number of gates, ports (in, out, inout),
aspect ratio, connectivity between blocks
Behind the scenes, SOCarchitect uses rudimentary technology information
for a given process technology. The question is whether this is
sufficiently detailed to yield well-behaved chip estimates as the
designer varies the block estimates.
DAC 2001 was their first public demonstration of the tool."
- Carina Chiang of Agilent
"Icinergy's SOCarchitect? - cool tool for Architects and feasibility
studies."
- Dan Clein, PMC-Sierra
"We are also interested in RTL timing/area estimators for our IP. I
was impressed with the Tera presentation, and would like to take a
closer look. In-Time appeared to be worth evaluating as well.
Mentor's HDL Detective (part of HDL Designer, derived from the former
Renoir, with Escalade technology) should probably be listed here. This
looks like a useful way to derive up-to-date block diagrams from RTL
and paste them into specifications (e.g. Word documents), as well as
a visualization aid. This can now be purchased separately from other
components (we really do not need an expensive GUI front end for
simulation, for example). An evaluation and purchase in the near
future is likely."
- [ An Anon Engineer ]
"InTime Software's Design Warrior
--------------------------------
Design Warrior aims to fix architectural issues in the RTL before
synthesizing the RTL. The idea is to stop using synthesis as an
analysis tool, since it's really an implementation tool.
Design Warrior has 3 parts:
- Technology Wizard, which builds a Design Kit from process
technology libraries.
- ProjectWizard, where a project leader sets up goals for the
project and evaluates progress.
- Designer's Desktop, which does RTL timing and area. It also
has work control flow.
Given the RTL, Design Warrior estimates the size, based on the
underlying process technology. It outputs RTL timing and area
estimates. InTime says the estimates should be within 20% of final
results, for area-based synthesis.
Design Warrior has a set of "work functions" that are based on
constructs in RTL. They generate a STAMP (now part of the Synopsys
Liberty format) for each work-function. Using the logical hierarchy
of the design, Design Warrior partitions the RTL into work-functions
for synthesis, and generates scripts to take this through synthesis
and static timing analysis. Synopsys' PrimeTime creates timing
estimates by performing static timing analysis on the design, which
is decomposed into work-functions represented as STAMP models.
Design Warrior provides constraints and custom wire load models and
"make" files for each block of RTL.
After synthesis, Design Warrior can output LEF and DEF, or Design
Warrior can do some additional floorplanning. InTime's Design Arena
provides a starting point for Design Warrior's floorplan. Before RTL
is available, Design Arena creates a top-level chip floorplan. It
creates an I/O frame, calculates the number of power and ground pads,
and generates power and ground topology for all the different regions.
Design Arena creates an initial floorplan, which is passed to Design
Warrior. Design Arena calculates the number of power & ground pads,
generates power & ground topology for all the different regions, and
passes it to Design Warrior. If Design Arena is not used, then Design
Warrior needs to have a starting point for the floorplan.
Design Warrior generates custom wire load models when the RTL floorplan
gets generated.
InTime relies on commercial tools, rather than duplicating their
functionality in their own products. This raises the question of what
InTime's "value-add" is. A synthesis tool (from Synopsys or Cadence)
is required. A static timing analyzer that supports STAMP (now part
of the Liberty format), such as Synopsys' PrimeTime, is required.
For a selected process technology, Technology Wizard can estimate the
maximum performance that can be expected, or, alternatively, for a
given frequency, how many stages of logic can be used between
flip-flops."
- Carina Chiang of Agilent
"Anything that George Janac does makes me pay attention. He came to
our company and gave a reasonable demo of DesignArena. I definitely
believe it has promise, especially if they do have an accurate RTL
estimation tool that comprehends different datapath architectures.
Definitely one to watch."
- [ An Anon Engineer ]
"InTime
------
InTime is claiming to have a kind of an RTL planning capability that
enables technology exploration at the RTL level. Looks like they
might be trying to enable designers to quickly forecast whether or not
a given technology/library will work for a piece of RTL. Trouble is,
I can't see what the InTime software was doing besides fronting for
Design Compiler, PrimeTime, and Silicon Ensemble. Maybe some
partitioning or Wire Load Model generation. Not much value-add."
- [ An Anon Engineer ]
"We use graph paper and pencils. Works great."
- [ An Anon Engineer ]
"The clock I got from InTime at DAC last year keeps the worst time I
have ever seen from a electronic timepiece. I have no idea how this
reflects on the company, but I feel it is ironic. My experience of
estimators is that they can be so far off that they are simply not
worth it. Frankly in a small company we don't have time or money
for such luxuries."
- [ An Anon Engineer ]
"We have just started looking at pre-RTL floorplanning type tools (as I
think of them) like TeraForm and InTime. Personally I'm a little
skeptical about the payback these offer."
- [ An Anon Engineer ]
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