( DAC 01 Item 4 ) ---------------------------------------------- [ 7/31/01 ]
Subject: Tera System's TeraForm
THE OTHER LINTER: This year, TeraForm has taken on a new, odd role as
a sort of linter crossbred with a design planning tool that's *very*
knowledgeable about backend issues like block-level placement. It
parititions your design for many "what if" assessments. They also use
as a fundamental part of their technology their own home-grown version
of DesignWare parts that they call 'TeraGates'. Curious & different.
"I like the idea behind Tera's TeraForm -- except that I found out
during a "private suite" session that it has some severe capacity
limitations (~1M gates). An awkward question brought up by an
engineer from another company. Hope they correct that."
- Kris Monsen of Mobilygen Corp.
"Tera
They offer a design planning tool which seemed a little lame. It does
some kind of auto-block creation, but has no power, clock or scan
capabilities.
They also do timing analysis of RTL which they claim is within 10-15%
of layout (pessimistic). Their floorplanner supposedly did 125 Kgates
in 7 minutes.
They claim to have worked on netlists up to 4M Gates. You can
optionally preserve your logical hierarchy. Their claim to fame
is "clean RTL sign-off". They are mostly used in an ASIC flow and
they swear the ASIC vendors are happy when the customers are
using Tera."
- [ An Anon Engineer ]
"Tera Systems's TeraForm
-----------------------
Tera Form decomposes the original RTL using a pre-characterized library
of "TeraGates" macros, resulting in a design with fewer elements to
analyze. Tera Form then performs a Steiner route and back-annotates
the info from the Steiner route into its timing analyzer to create
estimates. It partitions the RTL into blocks, which may differ from
the logical hierarchy. Tera Form uses the partitioned output to drive
the synthesis and placement technology.
According to Tera Systems, quick turnaround allows users to run lots of
"what if" analyses on different RTL designs.
Is Tera Form able to correctly identify critical paths in the RTL?
Tera Form has its own built-in synthesis, placement, and timing
capabilities. In contrast, InTime's DesignWarrior uses commercial
synthesis, placement, and static timing analysis tools.
Since Tera Form cannot perform the same optimizations on the design
that the Synopsys synthesis tools do, Tera Form may identify a critical
path that Synopsys' optimization algorithms can prevent from being
critical. Tera Form should find a superset of the critical paths,
which means you won't miss any, but you may end up examining paths
that aren't ultimately critical paths.
How well does the final design performance match the expectations set
by Tera Form? Correlation to estimates is Tera's greatest challenge.
At their DAC suite, they vehemently stated that it was a mistake to
try to see how close Tera Form's estimates were to the final chip
results. Given that their data sheet touts Tera Form's RTL area and
timing estimation capabilities, I couldn't follow their reasoning for
why the looking at the correlation of their estimates to final results
wasn't the right way to think about their tool, unless perhaps there's
a problem with the correlation?
Tera Form does not handle scan chains or clock trees. They recommend
building in additional margin to compensate for the additional delay
due to the scan chain and clock uncertainty."
- Carina Chiang of Agilent
"Tera Systems
------------
NEC is working with Tera to develop an RTL sign-off flow. LSI appears
to be working with Tera on something similar. The idea is to get RTL
that produces predictable physical design by exposing layout and timing
problems without having to learn physical design tools.
Tera partitions logic, primarily as small regions rather than large
hard macros. They can output hard macros, but it does not appear
to be the primary application of their tool. They do timing budgeting,
timing constraint partitioning, macro cell placement, and datapath
compilation. They build up custom wireload models.
They compile into aggregate gates they call Tera Gates. When they've
compiled a design down into Tera Gates, it is very easy to visualize
the data flow of the design.
Because a Tera Gate database is much more abstract than a gate-level
netlist, they can very easily implement nifty things like:
- Check for unregistered paths, unused ports, etc.
- Cross-probing from TeraGate netlist to TeraGate floorplan to RTL.
This is the tool LSI used to provide structural feedback/rule checking
on our first hierarchical database. This feedback later became
critical to time budgeting and hierarchical timing closure.
All in all, this tool looks like a way to perform alot of structural
analysis on a design before committing to a gatelevel netlist."
- [ An Anon Engineer ]
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