( DAC 00 Item 39 ) --------------------------------------------- [ 7/13/00 ]
Subject: Synopsys 'Physical Compiler (PhysOpt)'
THREE MONTHS LATER: Not a lot has changed with Synopsys in the 3 months
since I wrote the SNUG'00 Trip Report. That report gives you the collective
thoughts of what 39 customers saw at the Synopsys Users Group meeting which
took place March 13th to 15th. The data in this DAC Trip Report pretty much
matches the data in that SNUG'00 report. Synopsys still kicks ass in
synthesis, static timing, datapath, and scan/ATPG. They are still getting
their ass kicked in FPGAs, Scirocco, BC, and Eageli. And they're still
fighting 50/50 in Vera vs. Specman, VCS vs. NC-Verilog, and Formality vs.
Verplex. Also, SystemC is still in its infancy and controversial, like all
the other C EDA tools.
What has gotten interesting has been their Physical Compiler (PhysOpt) tool.
Click on http://www.deepchip.com/items/snug00-18.html and you'll find the
April 2000 score board of known physical synthesis tape-outs for everyone:
Magma, Monterey, Cadence PKS, PhysOpt. The data for everyone there, other
than PhysOpt, still holds true for July 2000. That is, no customer to date,
has yet to use Magma, Monterey, nor PKS to make a real chip. In the PhysOpt
table, add another tape-out in April by nVidea (the MV12 chip), plus a new
PhysOpt user tape-out by Unisys for July. The Unisys chip is a 1.5 million
gate, 0.18, IBM fab ASIC with three clocks at 100 - 133 - 200 Mhz. Ken
Merryman of Unisys is the designer. This means that PhysOpt now has a total
of 10 confirmed customer tape-outs as of July, 2000.
What's going on here is interesting not because there's just two more
tape-outs. Whoop-dee-doo. The PhyOpt tape-outs are neat, but they're not
the big news they once were because they're becoming common. And that's
what's interesting here. The fact that none of PhysOpt's rivals had a tape-out
for DAC (the biggest yearly show in the EDA industry) plus the fact that
PhysOpt tape-outs are becoming old news, shows that Synopsys now has a
measurable 9 month lead in the physical synthesis market. PhysOpt is just at
a more advanced stage than it's peers. To see this further, look at ESNUG
350 #2, 350 #4, 354 #3, 354 #7 and you'll see Synopsys technical support
reporting PhysOpt bugs & workarounds. They're doing it the the same way
they'd report DC, TetraMax, or VCS bugs. PhysOpt, at least for the Synopsys
hotline, is becoming just yet another tool they have to support.
I'm not saying PhyOpt is 'it', that they've 'arrived', or any such hooey.
(PhysOpt is catching too much grief from customers for not having its own
detailed router.) I'm just noticing that while Magma, PKS, Monterey are all
still wearing messy diapers and crawling around on all fours, there's a
dressed and walking PhysOpt on the bus alone going to first grade classes
at St. Mary's Elementary. Interesting.
"We're looking and open. We like PhysOpt integrated into the Synthesis
engine, but that doesn't make PhysOpt a winner for us yet."
- an anon engineer
"Synopsys is well ahead of the competition in the number of customers who
have actually produced chips with their PhysOpt, and that's what their
demo emphasized. Note that their physical synthesis flow does the top
level routing but does not do detailed routing (they don't sell a
detailed router). You get a placement out of their tool and then route
it with someone else's (Avanti or Cadence) router. They had previously
announced that they will be selling a detailed router by the end of the
year. Unlike some of their competitors (Cadence and Magma, for example)
they have no way of dealing with signal integrity problems since they
don't currently do detailed routing."
- an anon engineer
"Synopsys 2 stars (out of 3 possible)
Physical Compiler
This demo focused on the Physical Compiler tool from Synopsys which
attempts to address the timing closure problem prevalent in deep
sub-micron design. Synopsys now claims that 8 chips have "taped out"
using Physical Compiler and is now being supported by IBM, NEC, and
STMicroelectronics among others. Several examples were given
including a design done by NEC where a design with a 12ns clock which
had -8ns of slack (even after 6-8 iterations) was handled by PhysOpt
with only one ECO. The tool is intended to fit into existing design
flows and methodologies and is not "shackled" by being limited to
interworking only with other Synopsys tools. It works with other
floorplanning and CTS buffer tools along with other routing tools as
well. Of course, Synopsys has tools in these areas as well, but they
really emphasized that it was intended to interwork with other vendors
solutions. It should be noted that this tool is of indirect interest
to us since we no longer have a physical design flow and are essentially
fabless. However, we should pay attention to developments in the
physical design area to monitor what our silicon vendors have to offer.
It seems to me that some issues regarding scan insertion and the
subsequent scan stitching need to be handled better as this could
severly impact the effectiveness of the tool if not addressed up front.
In addition, it seems that chip design teams need to do a better job
upfront of specifying overall chip I/O timing parameters and initial
clocktree insertion delays to get the most bang out of the tool.
Designers familiar with Synopsys will like this tool because it uses
the same command set used by Design Compiler with only a few "extra"
requirements. Synopsys kept emphasizing that better results were
achieved by applying this tool at the RTL level instead of the
gate-level (after initial synthesis), but this is where I question
how the scan insertion and test optimization transforms can interwork
with the timing and placement engines within PhysOpt. However, with 8
tapeouts to date and the reductions in effort quoted, this tool seems
to be coming into its own as a bona-fide solution to the timing
convergence problem."
- an anon engineer
"We evaluated Synopsys Physical Compiler earlier this year. In the trial
we took the same design through two flows: 1) Synopsys DC followed by
Avanti Apollo, and 2) Synopsys PhysOpt. The two results ended up with
almost the same timing. Not that good, you may think. But it took us
about 6 months of work with flow 1, and about 2 months with flow 2. Our
conclusion was that PhysOpt is promising but still somewhat immature."
- an anon engineer
"Synopsys will win. Avanti has a chance because their layout really
works. Physical Synthesis will not be a mainstream technology for a
while so some of the others will lose interest."
- an anon engineer
"Physical Compiler is a joke until Synopsys has a detailed router. They
need to get Gambit (Route66) up. You can't do 0.18 cross-cap and SI
without kissme links to your detailed router. This isn't going to
happen with any Synopsys tool and a Cadence-Avanti backend."
- an anon engineer
"The third-party EDA vendor is my competitor. I'm not responsible for
taking care of my competitor's business."
- Gerry Hsu, Avanti CEO, on opening Avanti's Milkyway database to
customers but not to other EDA companies. ( EETimes 6/8/00 )
"I was wondering if you have heard anything about Synopsys' progress on
a detailed router. To my knowledge they said it should be out by year's
end, but I would think someone must be beta testing it soon if they do
plan to release it in the next 6 months or so."
- Jared Leon, Analyst at SBSF Capital Funds ( ESNUG 354 #4 )
"Synopsys - Route66 - Standard cell router offers equivalent features
like WarpRoute, completing the tool portfolio of Synopsys after
placement and top level routing."
- an anon engineer
"I saw the Synopsys Route66 demo under NDA. I wasn't very impressed."
- an anon engineer
"Synopsys PhysOpt seems to be the best choice, because of it's
compatibility with DC. The Magma approach sounds interesting, although
everyone already knew that the best approach would be to combine
Synthesis and Physical Design. But does Magma really work in real
designs? I suppose that Synopsys PhysOpt and Magma BlastChip will win
and that Cadence PKS will loose. Avanti will keep its position."
- an anon engineer
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