( DAC 00 Item 15 ) --------------------------------------------- [ 7/13/00 ]
Subject: Synopsys Vera, Verisity Specman/'e', Chronology RAVE, SynaptiCAD
THE PERFECT STORM: The three way stormy battle between Verisity's Specman,
Synopsys VERA, and to a lessor extent, Chronology's RAVE, shows no sign of
concluding any time soon. It might moot though, if C/C++ kills off the
whole concept of proprietary functional testbench generator languages.
"I made the mistake of scheduling the Vera and Specman demo's back to
back. I can't for the life of me tell you the differences between
the two tools. They even spent 5 minutes in each "demo" talking about
the Dataquest numbers. Based on these two "demos" the main difference
between the two tools is that the Synopsys people say the Dataquest
report is old and out of date and the Verisity people quote the report
as gospel. Verisity had an alter in the back of the booth where they
burn incense to the Dataquest Gods."
- an anon engineer
"Rumor is that actually Synopsys is backing away from VERA, and putting
emphasis on SystemC (which on it's own will kill VERA). Lets see us
substantiate that. In not so many words a Synopsys pre-sales tech guy
admitted this to me."
- an anon engineer
"I got a real kick out of Synopsys trying to have something to say to
respond to Verisity's claim of a Dataquest 77 percent market share.
Bottom line to Synopsys' claim about having more installed seats of
Vera than Specman is that there are a lot of Synopsys sites with bins
of free licenses floating around. You can have the installed license
specsmanship award, Synopsys, but I'd look hard and long at the product
people are actually spending $$ on.
Beyond the "why I'm best" chest pounding, I still am looking for an
articulation of a solution that allows me in mixed VHDL/Verilog to
verify major functional blocks in unit level test benches, then also
migrates directly to verification at the system (chip or multichip
'board') level. I've yet to see a compelling marketing (or
engineering) presentation of such a solution. A full top-to-bottom
verification solution still seems to require a lot of internal
innovation. I'm waiting to see some reality in all the talk about
virtual verification."
- an anon engineer
"Chronology 2 stars (out of 3 possible)
QuickBench
Quickbench is yet another testbench authoring tool which allows one to
build testbenches at a higher level of abstraction. Quickbench provides
a layered approach whereby Bus Functional models called "transactors"
can be derived from timing diagrams captured by the designer using the
TimingDesigner tool (we already use TimingDesigner for documentation
purposes for drawing waveforms in our databooks). A special language
based on Perl called RAVE can be used to interact with the transactors
and drive stimulus or compare captured results. Most temporal activity
is performed in the transactors while the higher-level 0-time
generation/comparison is done via the RAVE language. The tool seems
comparable to some more well-known solutions from others. However, it
does not yet support C/C++ support but the claim is that it is on their
"roadmap" for future products. No functional coverage capability is
provided yet either. I've rated this tool only 2 stars because of two
things; the lack of C/C++ support and the fact that it requires
TimingDesigner to generate the BFM models. Like other tools, there is
another proprietary language to learn even though it is based on Perl.
But I did like this tool because it appears to me that it could be
useful for block designers in creating a more robust block-level
verification environment.
As chips grow more complex, chip-level testbenches can become huge and
require enormous amounts of CPU power to to run. I believe that in some
cases, we should now look at generating more sophisticated sub-system
testbenches to conduct more of the verification at lower-levels. The
advantage of Quickbench is that more ASIC designers are probably
familiar with Perl than with C++ and it may be easier for them to use
this tool."
- an anon engineer
"The biggest lie I heard at DAC was that VERA is the number 1 test bench
automation tool. It was by a Synopsys sales person with an acompanying
slide in a Covermeter Demo. They never even bothered to offer data
(like VERA had the most sales in Fiji or something), they felt it was
true because they said it was true. Arrogant."
- an anon engineer
"Chronology
- QuickBench will automatically generate bus models and test harness
that follow our methodology from bus cycles captured using a
timing diagram editor (old stuff).
- Rave is their verification language and is an extension to PERL.
Sits on top of the test harness and calls Quickbench-generated
transaction procedures. A nice enforcement of proper testbench
architecture practices.
- Good random generation but no functional coverage. If RAVE can
stand alone, without the QuickBench-generated harness, and
interface to user-written bus-functional models or directory to
the bit-level interfaces (allowing one to write bus models in
PERL), it can be a serious contender to VERA & Specman.
PERL suffers from the same controllability and communication problems as
C/C++ for parallel threads."
- Janick Bergeron of Qualis Design (VG 1.13)
"I don't think any of the new testbench generators, Testbuilder from
Cadence, iControl from iModl, Testbencher Pro from Synapticad, or
Quichbench from Chronology, are quite mature enough yet. We're going
to need something like this soon, and I think we're going to stick with
Specman and Vera for our eval. Testbuilder and Quickbench look like
the best of the new ones, while Testbencher Pro and iControl are simply
not there yet."
- an anon engineer
"Verisity has the majority of this market, with Vera in second place.
Verisity sells Specman, a tool that takes a description of your design
in their "e" language and automatically generates test benches. The e
language was drastically revised last year because it was very hard to
master. The big problems with selling this tool are that your users
have to learn another language and now have two versions of the design
(RTL and e) that they have to keep in sync. Acceptance has been slow.
They have come up with a brilliant new business model. They have teamed
with IP providers. Soft IP (i.e. RTL code) is often designed to be
customizeable by the user. The question is - how do you know you
haven't screwed it up while customizing it? ARM, MIPS, TI and LSI now
ship IP with a free copy of "invisible Specman". The IP provider has
described correct function of the IP in Specman, and the buyer then gets
a limited license to check his modified design. This way, the buyer
doesn't need to learn e or describe the design for the tool. Mentor and
Cadence are now licensing the language - looks like it may become a de
facto standard."
- an anon engineer
"Well, I'm hoping that Vera and Verisity will be around next year, but
I'm not too sure with that whacky C push going on."
- an anon engineer
"Our colleagues in [ deleted ] already use Specman and we are going to
introduce it soon. The fact that Mentor and Cadence are also adapting
tools for the use of the 'e-language' encourages me that this language
is a success. I unfortunately forgot to look at Vera at DAC, though it
was my intention. 'Rave', I would forget about."
- an anon engineer
"Synapticad: Most improved. Last year their stuff was sort of primative.
The Verilog that it spit out was pseudo VHDL with some the negatives of
VHDL. No fork and join and stuff. They have cleaned up and added alot.
Does not quite follow the Client server methodology, but looks like it
could easily be done. I bet the implement it soon. The BRM's have an
entity/arch pair for each abstracted task (write, read) and then those
are put in a package. No upper level vera/E type code to do thing. They
use perl to do stuff at the top level. The do not use records to pass
signals, but they do have a group of signals to pass through info to
sync things up. No VHDL fork and join implementation. Use a harness
and testbench with no I/O."
- Peet James of Qualis Design
"SynaptiCAD - has several useful tools for producing Verilog test benches
from timing diagrams, for translating HP logic analyzer data into
stimulus vectors or timing diagrams, and for generating data sheets.
They also have a Verilog simulator. Pricing is generally a few $K."
- an anon engineer
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