( DAC 00 Item 14 ) --------------------------------------------- [ 7/13/00 ]
Subject: The Superlog Alternative To The C-Or-Verilog/VHDL Wars
NOT C, NOT VERILOG, IT'S SUPERLOG: Mixed in with the C-or-Verilog/VHDL
wars is a third option that should be noted: Co-Design's Superlog. Superlog
is a new HDL that's an extension of Verilog. Superlog was announced at last
year's DAC and I'll be the first to admit that I was part of the crowd
laughing at the idea of Yet Another Hardware Description Language. I was
in good company. A lot of people doubted the need nor use of a new HDL.
But now that it's become more real, a number of doubting designers are
giving Superlog a decent second look because not a replacement for Verilog,
but a superset of Verilog. That is, Superlog runs legacy Verilog code as
is; Superlog just allows new code to be written that does *more*. Now, the
barrier to acceptance of Superlog has moved on to the more practical
concerns of openness and no tools around to synthesize it.
"I spoke to the Superlog people about C and Verilog. They have a
different approach to C, extending Verilog to give C features. This is
easy from the HW person's perspective, while still letting SW code run
with it. They plan to make it open once they have established some
support with a few customers."
- an anon engineer
"The SystemSim tool from Co-Design looked really cool. I got to see some
real Superlog code, too. It seems like a nice language for doing high
level system design -- the only thing that has me scared is that being a
new language, an INCREDIBLE barrier exists for it to penetrate people's
world -- "where are the tools?" It will suffer from the same problem
VHDL suffers from, namely: "Well, you can *model* that in VHDL, but you
can't synthesize that code." for many years I fear."
- an anon engineer
"We are doing a lot of simulation with Verilog-XL and we were a Beta site
of Superlog. The solutions seams to work fine and even the combination
with our C++ library worked. But they still have to do a lot of work,
especially for making the whole thing synthesizable. I personally
believe that a combination of Verilog and SystemC would have more
benefits, because I think that with Superlog you are still stuck at the
event-driven simulation approach."
- an anon engineer
"I've looked at a number of the C-like EDA products, but have not had an
opportunity to be involved in a project using them yet. But after
looking at what these C-like EDA products have to offer, and at their
syntax and semantics, SuperLog is the only product that I want to try.
SuperLog takes what HDL's do best, and enhances the capabilities,
instead of trying to replace the HDL with C. With SuperLog, I can
model hardware the way hardware works, and if -- and only if -- I need
more abstract programming, I can also access the capabilities of C. I
suspect the next generation of Verilog will take a very similar approach
as SuperLog."
- Stuart Sutherland, independent Verilog PLI consultant
"Superlog is great (Combining VHDL constructs w/ Verilog and simplifying
Verilog for FF's, etc.) We will most likely use it in our next
generation uP."
- an anon engineer
"For modeling, C is not yet fully usable and way to high level for uP/uC.
For Testbenches, C is ideal and for cycle accurate C-models. Superlog
is the best way to go right now (and not too high for most designers.)"
- an anon engineer
"Since we use VCS, I got the update for that, but didn't look at other
simulators. I like where Synopsys is going with VCS. Faster, as
always. Supporting C, for tasks/functions and modules, without PLI.
I think Superlog looks very nice. They cleaned up Verilog in a lot of
good ways. I also like Co-Design's simulator, SystemSim. It integrates
C nicely. It can do interpreted or compiled, but the speed tradeoffs
aren't as bad as normal. However, I don't think it's quite compeling
enough to dump our existing VCS investment here. Now, if I were
starting from scratch at a new company, they'd have a serious shot at
selling to me."
- an anon engineer
"Superlog has some interesting functionality that makes it closer to our
own C++-based simulation environment. As such, it may be a better
middle-of-the-road solution between existing Verilog, and the
SystemC/CynApps approach. I heard a lot of pooh-poohing about Superlog
from other hardcore Verilog users, though."
- an anon engineer
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