( DAC 00 Item 12 ) --------------------------------------------- [ 7/13/00 ]
Subject: Synopsys NDA Suites On VCS, the PLI, and C
PLAYING BOTH SIDES: While there's a nest of new C-based EDA tools still
trying to prove themselves, if you went into the Synopsys NDA suite at
DAC you would have seen how their VCS R&D guys have crafted VCS to be
able to read in C *without* going through the PLI. (Although bypassing
the PLI did seem to piss off one consultant I know...)
"NC-Verilog has caught up with VCS in performance and far surpassed VCS
in reliability. As a consultant and as a trainer on Verilog HDL and
PLI, I work with a lot of companies, both large and small. Some of the
large companies I work with are dropping VCS and switching to NC-Verilog
as their main simulator. Performance is part of the reason for the
switch, but IEEE 1364 compliance is the big reason. Despite all the
marketing and sales bull from Synopsys, VCS is not even close to being
IEEE compliant. VCS was created following the 1990 OVI Verilog
standard, and has never been updated to the IEEE 1364-1995 standard. In
the area of PLI support, VCS is the worst product there is."
- Stuart Sutherland, independent PLI consultant
"I attended Synopsys' DAC presentation describing their new Direct-C
interface being built into VCS. This is long overdue: replacing the
bulky slow PLI interface with a native interface which will allow
calling C or C++ functions directly from Verilog source, allowing easy
string manipulation and file I/O.
Their "CModule" portion allows instantiation of C or C++ modules right
in the Verilog code. They have added sufficient concurrency (such as
"always @") to allow C/C++ system modeling to be used in a hardware
context. Scheduling and building the golden reference will remain a
challenge, but at least this gives us more flexibility and performance.
Synopsys claims these functions will use VCS's direct kernel interface,
be an integral part of VCS, and be delivered as a free upgrade. We
will certainly give these new features a try."
- an anon engineer
"Here are my obeservations about the VCS advanced technology demo.
We are users of Verisity's Specman tool and last time we bought
simulators we did not purchase any more VCS licenses, although we
do use our current VCS licenses. I think to get the simulation
performance to the level that is needed to the next generation
chips, we'll need two things:
* Both the Chip and the Test Environment are in the same
language (C/C++)
* Make the interface between the high level verification
environment language and the Verilog invisible. Both from
a performance and ease of use perspective.
The second item above is what Synopsys' VeriC/DKI interface attempts to
tackle. In a nutshell the new interface extends the Verilog language
(non-standard) to allow the user embed C functions in two ways. One
is to create "extern" functions which can be used to assign to Verilog
registers. The other is the ability to create "cmodule" which is to
have a Verilog module front end (inputs, outputs, inouts) with a C
backend. This allows the user to create pieces of C code that know
about time. Both of these use VCS' Direct Kernel Interface (DKI) which
if I understand this correctly allows C object files to be directly
linked with Verilog objects. They have ported their Covermeter tool to
use this interface and it appears that they have gotten significant
performance improvements over Covermeter with a PLI Interface.
This seems to be a very exciting technology and might be able to give
the people talking about a pure C++ environment a run. Also, as some IP
modules start to be developed VCS now has a very good story on
integration of mixed Verilog/C++.
That being said, I was extremely dissapointed that when I asked if any
outside PLI vendors were looking at porting their tools to use the
VeriC/DKI interface, I was met with blank stares. It was almost
inconceivable to them that someone would use a non-Synopsys verification
tool. I can understand that some of the companies (Verisity) directly
compete with their product offerings, but if they were serious about
finding designers to test out these new technologies, some the outside
tool vendors would be perfect. This would also give them a sales
advantage to say that TOOLX works better with VCS that NC-Verilog. In
general Synopsys seems to think that they have the same advantage in the
verification space as they do in the synthesis space, and without other
PLI tool vendors asking Cadence for a similar interface, they will never
be able to push this foward as a standard.
If Synopsys had said that they were working with outside tool vendors to
get them to use this interface I probably would have voted it one of the
most interesting Suite Presentations at DAC. As it is, that award goes
to Verisity. Last year they presented technology that they delivered in
the form of their interface to Cadence FormalCheck which looks pretty
cool and allows E code to be parced for Assertions for FormalCheck.
This year they presented a tool called Coverage-Maximizer which if it
works will analyze your Verilog source code and your E environment and
do two things: 1) Suggest Functional Coverage points within the design,
and 2) using data collected on those points create an E file that will
constrain your environment in a new test to attempt to hit those points.
This technology is very green and it is unclear how well it will scale
to very large test environments, but it could be really useful to
automate test writing."
- an anon engineer
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