"Those who fail to learn from history are doomed to repeat it."
- Winston Churchill, British PM during WW2 (1874 - 1965)
( ESNUG 591 Item 1 ) ---------------------------------------------- [01/13/22]
Subject: Dan Joyce's 16 + 29 == 45 gotchas if you FAIL to do gate-level sims
DAN JOYCE RUINS EVERYTHING: It was roughly 5 years ago back in 2017 when, as
a chip designer (or chip verification guy), we all began think to ourselves:
"Yay! At least now I don't have to do any more of those pesky gate-level
Verilog simulations! They're a pain-in-the-ass to do and a waste of time!"
That was until Dan Joyce, then a chip design contractor at Samsung Austin,
described how he had done 22 chips in his career (at that time) and he had
"always found a chip-killing bug with gate-level simulations that formal,
STA, ABV, lint, LEC, and emulation had failed to catch."
---- ---- ---- ---- ---- ---- ----
The centennial 2017 Dan Joyce analysis that brought back gatesims
First, the 16 bug types only found with gate-level simulation:
Dan Joyce's 16 bug types only found with gate-level simulation
---- ---- ---- ---- ---- ---- ----
Then 6 tips on how to choose and set-up cost-effective gatesims
Dan Joyce's 29 cost-effective gate-level simulation tips (pt 1)
---- ---- ---- ---- ---- ---- ----
Then 10 more tips on X's, clock glitches, SDF timing checks, etc.
Dan Joyce's 29 cost-effective gate-level simulation tips (pt 2)
---- ---- ---- ---- ---- ---- ----
Finally 13 more tips on regressions, probes, BFM's, asynch clocks, archives, etc.
Dan Joyce's 29 cost-effective gate-level simulation tips (pt 3)
---- ---- ---- ---- ---- ---- ----
And then the 157 + 21 == 178 user responses to Joyce's 29 tips...
157 positive and 21 negative user comments on Dan Joyce's GLS post
---- ---- ---- ---- ---- ---- ----
And then Dan Joyce's personal guarentee ...
Which begs the question: "did anyone ever actually get to collect on
this free steak dinner from Dan?"
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