( ESNUG 590 Item 01 ) --------------------------------------------- [03/17/21]
Subject: An accidental report card on Anirudh's HW accelerators/emulators
AN ACCIDENTAL REPORT CARD: Every year as a result of DVcon, I get a flood of
verification related questions. It's a natural byproduct of that conference.
Usually it's EDA users asking me about some specific verification tool; and
I try to do my best to answer them.
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EDA Users
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Wall Street Analysts
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But there's always a few Wall Street guys peppering me with questions, too.
One of them asked me: "is it true that Synopsys ZeBu and HAPS combined sales
peaked in CY 2019?"
My initial reply was: "Sorry, but I don't know." and I left it at that.
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But this Wall Street guy's question got me curious.
I started digging in SNPS and CDNS Earnings Reports. Sure enough buried
deep within an earnings Q&A was:
"We had a really good year [2020], good year for good quarter and good
year [2020] for hardware and it [2020] was down slightly versus a record
year in 2019, but nonetheless, [2020] a really strong revenue year
for us."
- Trac Pham, Synopsys CFO, SNPS 4Q20 earnings call (12/02/2020)
There it was. By their own public admission, SNPS HW sales peaked in CY2019.
Time to dig through the analysts reports to see if they confirmed this.
"... we've inferred [SNPS] hardware revenues of more than $70 million,
up over 30% year/year and up over $15 million from 3Q20 (perhaps
including some incremental demand from its largest customer); if correct,
this would imply FY20 HW revenues of about $220 million, down slightly."
- Jay Vleeschhouwer, Griffin Securities Synopsys Report, Q4 FY2020
"Verification HW, was very strong in 4Q, but down slightly y/y for F20."
- Rich Valera, Needham & Co. Synopsys Report, Q4 FY2020
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Now even *more* curious, I started pawing through all the Wall Street data
(6 x 2 x 16 == 192 analyst reports + 32 earnings calls == 222 documents) to
see if I could puzzle out SNPS vs. CDNS HW sales -- who was ahead and who
was behind? After tons of pawing, 2017 to 2020 quarterly HW sales came to:
which was zig-zag city!
But take the same data and annualize it came up with:
Showing a clear trend of CDNS HW (11.6% CAGR) outpacing SNPS HW (1.6% CAGR)
by a 10.0% CAGR.
Then I remembered that Anirudh became president of Cadence in 2017 -- making
this an accidental report card on Anirudh's HW performance.
My congrats go to Anirudh.
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IT'S ALL ABOUT THE CHIP
The untold story here is it's the custom processor chips that are driving
this -- because they're the true engines behind the Cadence and Mentor
emulation/acceleration HW boxes.
Yes, the CDNS/MENT/SNPS HW guys can squeeze out some non-trivial speed-ups
and capacity gains with software updates on their boxes; but those max out
to a total 10% to 30% boosts (at most) for the life of the HW box.
The exceptional "2x speed-up" and "double the capacity" gains only happen
when a totally new custom processor chip is introduced -- which is why
whomever has the newest chip at the new node takes ~80% of the emulation
sales for the following 24 to 36 months after the new chip is released. The
2nd new chip at the same mode grabs ~60% backlash sales following its launch.
A new uP chip -- especially at a new node -- is the difference between riding
a racehorse and driving a Lamborghini in the Monaco Grand Prix.
Yesterday's technology was great for yesterday's emulation/acceleration, but
it's not enough for emulating/accelerating today's chips. In 2010, Cadence
launched Palladium XP with its new 65nm uP. Then in 2012, Mentor launched
Veloce 2 with its new 65nm uP. Then in 2015, Cadence launched Palladium Z1
with its new 28nm uP. Then in 2017, Mentor launched Veloce Strato with its
new 28nm uP -- with each new chip at the new node taking ~80% -- and the
2nd new uP chip at the same node garners 60% of the new EDA HW sales.
And ironically, the only continual loser here is Synopsys -- because Zebu
and HAPS hardware is tied to whatever Xilinx decides to sell. Aart's ZeBu
boxes use Xilinx FPGAs as their emulation processor; and his HAPS boxes use
either Xilinx or Altera FPGAs as their processor. Problem is Intel bought
out Altera (and Altera has languished since); and AMD just acquired Xilinx
(promising that Xilinx might languish, too, if AMD wants Xilinx for focus
on the I/O-speed-at-all-costs Server market instead of the Big Ass Capacity
FPGA For Emulation/Prototyping/Acceleration market.)
Search for "CapEx on data center investment" and you'll see it's around
$137 billion -- while Emulation CapEx is around $750 million -- so it's
not all that difficult to see where AMD will direct Xilinx R&D to go.
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TIPPING POINTS TO WATCH FOR
There are 3 possible futures to look out for.
- If Cadence announces a NEW chip while Mentor is still on their OLD
chip -- Happy Anirudh, Sad Ravi, and Sad Aart.
- If Mentor announces a NEW chip while Cadence is still on their OLD
chip -- Sad Anirudh, Happy Ravi, and Sad Aart.
- If *both* Mentor announces a NEW chip and Cadence announces a NEW
chip -- Happy Anirudh, Happy Ravi, and Sad Aart.
The only constant in all these EDA HW box futures is "Sad Aart".
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TOO LONG; DIDN'T READ
Anirudh kicked HW ass in his 3 years at the CDNS helm with a 11.6% CAGR vs.
Aart's sickly 1.6% CAGR in HW -- but that's *only* from SW updates to his
Palladium and Protium boxes. Whomever launches a NEW HW uP chip (CDNS or
MENT) will steal 80% of the upcoming 2021 HW sales. And either way, Aart's
HW sales suffer because his uP's are sadly tied to Xilinx and Altera.
- John Cooley
DeepChip.com Holliston, MA
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Related Articles:
Sawicki and Anirudh on Veloce2, Crystal 3, Palladium Z1, Zebu4
CDNS Protium crazy fast "Palladium-compiles" #1a for Best of 2019
SCOOP -- will the new MENT Veloce Crystal 3 chip crush Palladium?
Jean-Marie warns Synopsys Zebu needs 9X more "warm bodies" to run
A surly Jean-Marie sasses Cadence Palladium and Synopsys EVE Zebu
Frank on Lauro missed Palladium job throughput 3X faster vs. Zebu
The 14 metrics - plus their gotchas - used to select an emulator
MENT bigwigs say Veloce 2 will pass CDNS Palladium by end-of-2012
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