( ESNUG 588 Item 15 ) --------------------------------------------- [03/27/20]
Subject: Costello on his custom RISC-V Montana vs. CDNS Rocketick Intel
DAC'19 Troublemakers Panel in Las Vegas, NV
Cooley: Costello! All right. We've been hearing about Montana for,
gosh, how many years now?
Costello: 7 at least. You probably didn't hear about it 7 years ago.
I did.
Cooley: Is it soup yet?
Costello: Nope, not soup yet. It's not soup. And one of the reasons
why, is we made a choice in the last year.
Last year, we demonstrated, here, an Altera version of a
custom processor. And as we looked at the next generation,
we decided that was a silly way to go and we are going with
a customized RISC-V processor as the new base for it.
Cooley: You change architecture all together? You went you went
to RISC-V?
Costello: Yep. Went to RISC-V. Yeah. And the reason was when we looked
at the overall, required set of tools - and again SW and HW set
of tools -- required to get an accelerator-processor done of
that sophistication -- it was a way better bet to go with
RISC-V. Better processor for us, better support.
A customizable processor by the way! If it was just "you get
what you get" [like an Intel general purpose CPU] it would have
been crap.
Cooley: Are you pairing back the architecture? Like what Naveed was
talking about?
Costello: Yeah, exactly.
Cooley: Okay.
Costello: And so, you know, we get to make what we want out of it. We
use the instructions we want and don't use the ones we don't
want -- and yet get all the support around with it.
It was kind of a no-brainer choice to make that switch for the
long term, you know, we made a great first prototype of it as
a complete custom processor. For a long-term product, this
[RISC-V approach] is a much better choice.
Cooley: You're making your own core? Or are you using a SiFive core?
Costello: We are making our own RISC-V core because you start with
the base. Again, it's an open source thing. We start with a
base and then we modify.
Cooley: What tools are you using?
Costello: For our own development?
Cooley: Like validation, verification, place and route... All that
fun stuff. Are you using Cadence tools?
Costello: [pause] [audience laughs ]
[audience laughing because Joe Costello was
Cadence CEO from 1987 to 1997 while making it
the largest EDA company of its time.]
Cooley: Are you NOT using Cadence tools?
Costello: [pause]
Costello: No, we're using Mentor. [laughter]
But we'd be welcome to take anything from Lip-Bu and Anirudh.
too.
[more laughter]
Cooley: I didn't hear clearly. Who's tools are you using?
Costello: Mentor's.
Cooley: Oh, the Tanner stuff?
Costello: Not everything.
Cooley: You gotta do place and route? You got to do all sorts of stuff.
Costello: We haven't done place and route yet, because remember, we're
doing FPGA right now.
Cooley: Okay, so it's early stuff.
Last year we were talking about you and Rocketick. Why should
I buy ... well, I can't buy your stuff now ...
Costello: You can't buy my stuff yet.
Cooley: Alright. But aren't you just going to be another Rocketick
when you're done?
Costello: No, Rocketick is a performance improvement on the Intel CPU
architecture, which is really important. Optimize the use
of Intel parallel processing as much as you can.
However, it's a dead end. You can only go so far with
performance improvement with Intel and parallelism -- it's
just not going to go that far.
It's just like the rest of the world. The reason that Google
has thousands of guys building TensorFlow chips is because you
can't get there with a general-purpose processor, whether
you're using Intel or Nvidia. You have to build a TensorFlow
processor.
And we're doing the same thing. This is the whole wave behind
the SiFive and the custom processor movement.
The only way to improve performance in the next decade is to
build a custom processor. And that's what Montana is doing
for SystemVerilog.
Nothing wrong with Rocketick (Xcelium) software.
Maybe they'll import it to our Montana processor. [laughter]
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