( ESNUG 583 Item 1 ) ---------------------------------------------- [05/24/18]
Subject: Yorgos schools Cooley on Helic vs. PT-SI, CLK-DA, HFSS, and Star-RC
Instead, despite this marketing mix-up, Helic is doing something far
crazier. Instead, Yorgos is going after Aart's Primetime-SI franchise
in crosstalk delay and noise -- by Helic doing clever RC-extraction...
... the very niche where Isadore Katz of CLK-DA just went out of business
3 months ago trying to do. How delusional is Helic to try this now???
- from http://www.deepchip.com/items/0574-01.html
... From my simple understanding, Helic is like PrimeTime-SI and CLK-DA,
but by adding inductance, Helic is far more accurate than both of them
at 7nm. ...
- from http://www.deepchip.com/items/dac17-07.html
From: [ Yorgos Koutsoyannopoulos of Helic ]
Hi, John,
This is the second time you have compared Helic ElectroMagnetic (EM)
crosstalk tools with Primetime-SI and CLK-DA. That's just crazy!
PT-SI and CLK-DA are timing analysis tools for digital designs. They only
analyze electrical coupling or noise. They use the RC parasitics of signal
nets, plus the mutual capacitances between neighboring signal nets. They
do NOT extract all surrounding metals in the layout. And more importantly,
they do not extract self-inductance nor mutual inductance.
By contrast, EM crosstalk is the unwanted interference caused by electric
and magnetic fields of one or more signals (aggressors) affecting another
signal (victim). Today's SoCs are a dense mixture of digital, analog and
RF blocks drowning in EM crosstalk. Analyzing it requires a full 3D RLCK
extraction of the signal nets involved together with all the surrounding
structures present in the layout.
Focusing on the neighborhood of a victim signal net works well for tools
analyzing electrical capacitive coupling such as Primetime-SI. However,
magnetic fields can travel along relatively large loops formed by
structures outside the immediate neighborhood of a victim signal. This
means that we must extract large chunks of the design layout.
This table below summarizes the differences between timing analysis and
full EM Crosstalk analysis.
As 14nm and below, we've seen increased demand for EM crosstalk analysis.
Here's what's driving it:
- Speed: Clock frequencies continue to rise to 5-10 GHz. Also, data
rates are escalating up to 10-100 Gbps. Parasitic inductance and
inductive coupling that were previously OK to ignore, can no longer
be ignored at these speeds. The faster the speed, the louder the
crosstalk. It is important to note that a clock signal with fast
rise and fall times contains very fast harmonic frequency components.
A clock running at a few GHz with 100 ps rise time has a 5th harmonic
frequency component running at 50 GHz.
- Mixed Block Integration: The continuous shrinking and placement of
high-speed digital, analog and RF blocks near each other creates
ripe opportunities for EM crosstalk.
- Low Power: The new lower voltage (VDD) levels driven by lower-power
trends exacerbate EM crosstalk.
- Cluttered Architectural Trends: Most of today's SOCs have multiple
serial lanes, multiple high speed PLLs and clock networks, plus
integrated transceivers and advanced packaging such as WOW. All
of these increase the risk of EM crosstalk.
Now John, since you erroneously compared Helic to the wrong EDA tools, let
me now to share how Helic compares to two relevant classes of EDA tools.
---- ---- ---- ---- ---- ---- ----
First, here's Helic Exalto vs. Ansys HFSS tool, considered by many as the
reference 3D EM crosstalk tool on the market.
As the table illustrates, Ansys HFSS cannot handle large designs on silicon,
but does well in package and PCB. The real life silicon capacity, memory,
and runtime constraints often lead to HFSS dropping important (under 16nm)
details about the design and its surrounding environment. This can hide the
effects of crosstalk leading to the wrong conclusion.
In contrast, my Helic engine models all the major layout structures:
- power/ground nets,
- critical signal routing,
- bulk silicon substrate,
- power grid de-coupling caps,
- bump pad layers,
- seal rings, and
- even package layers.
Exalto's capacity and it's intelligent handling of design layout details is
crucial to exposing real EM crosstalk. The Helic engine can also handle
layout-dependent effects in under 16nm nodes. Ignoring these effects can
impact extraction quality and can lead to erroneous results.
(Yes, John, high accuracy is vital in EM crosstalk analysis, however, this
level of detail is required only in critical parts of the layout, and not
everywhere. Helic automatically operates in a hybrid extraction mode to
get high-accuracy and high capacity -- while still performing at reasonable
speeds. HFSS can only do this only in package and PCB -- not silicon.)
---- ---- ---- ---- ---- ---- ----
Second, now let's compare Helic Exalto vs. Cadence/Mentor/Synopsys general
purpose extractors with their "extract inductance" option thrown in.
These Big 3 general purpose extractors are great for general RC extraction,
but they fall down on EM crosstalk problems. From its inception, Exalto
has been coded to work *with* Star-RC, Quantus, and Calibre PEX to augment
doing full EM-aware extraction -- and *with* Cadence Innovus and Synopsys
ICC/ICC2 PnR flows -- for faster and more accurate EM crosstalk sign-off.
Our next steps at Helic are: to more tightly integrate to SPICE tools
(BDA AFS, HSIM, HSPICE, FineSim, Spectre) for faster model simulation
runtimes -- and to make Helic Exalto more tightly integrated within the
Primetime and Tempus STA sign-off flows.
- Yorgos Koutsoyannopoulos
Helic Santa Clara, CA
P.S. I hope this clarification doesn't confuse you too much, Cooley. :)
---- ---- ---- ---- ---- ---- ----
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