( ESNUG 567 Item 1 ) -------------------------------------------- [02/16/17]
Subject: SCOOP -- will the new MENT Veloce Crystal 3 chip crush Palladium?
From: [ John Cooley of DeepChip.com ]
Just in time for the upcoming DVcon'17 conference 12 days from now, my spies
report that Wally & Greg's emulation guys are just about to launch a brand
new family of emulation boxes called "Veloce Strato" that's based on their
newly completed Crystal 3 microprocessor chip.
IS HISTORY ABOUT TO REPEAT ITSELF?
Last time this happened was 6 years ago back in 2011 when CDNS Palladium XP
sales were going gangbusters -- that is, until MENT came out with its then
new TSMC 65nm Crystal 2 processor chip -- which suddenly switched the bulk
of the emulation market back over to MENT Veloce in 2012. By mid-2012:
"Based upon publicly reported numbers, that run rate puts us on
track to achieve the #1 market share position this year in the
rapidly growing emulation market."
- Wally Rhines, CEO, Mentor Earnings Call (05/25/12)
"Rich, we think that, well, when we exit this year, that our revenues
will be such that we can claim a #1 market share in emulation; so
there is no slowing in the pace of bookings in the business or
our shipments."
- Greg Hinckley, CFO, Mentor Earnings Call (05/25/12)
Did you get that? That was Wall St. speak by Wally & Greg saying their
new Veloce 2 sales would overtake CDNS Palladium sales by Dec 31, 2012.
And it did!
And by DAC 2013, MENT Veloce 2 was the #2 Cheesy Must See thing at that DAC:
2.) Wally and Greg shocked the EDA world when 11 months ago they said
their Mentor Veloce 2 will pass Cadence Palladium by end-of-year.
(ESNUG 510 #7). Snooping I found out that Veloce 2 has roughly
the same cost-per-gate, same compile time, same debug visibility
as Palladium. "But for identical capacity it's 1/4 the size and
uses 1/4 the power and cooling Palladium does. Veloce Codelink
runs software debug 20X faster than Palladium's JTAG probes.
Veloce Testbench Xpress ~4X faster simulation acceleration than
Palladium." Veloce 2 even has a 2 billion gate box installed!
Broadcom, Mitsubishi, NXP, ST, Trident, ZTE, HiSilicon uses it.
(booth 2046) Ask for Jim Kenney. Freebie: stuffed bat
- from http://www.deepchip.com/gadfly/gad053013.html
So let's fast forward to today. 16 days ago in his Q4 2016 earning call,
CDNS CEO Lip-bu Tan added Qualcomm and Cavium to his Palladium public
users list of Nvidia, Huawei, TI, Broadcom, AMD, Nvidia, Freescale, Samsung,
Mediatek, Sharp, and MicroSemi. On top of that he said:
"We are pleased to report that Palladium Z1 had a phenomenal full
year on the market. Total hardware revenue surged to a record high.
We gained 29 new Palladium Z1 logos in 2016, 11 of which were system
companies, and this is the fastest adoption of a new emulation
system in Cadence history. ... Customer enthusiasm for the
Palladium Z1 led to a record year for hardware."
- Lip-bu Tan, CEO, Cadence Earnings Call (02/01/17)
But now that Wally & Greg just launched their new Crystal 3 uP chip, and
knowing that the emulation business is based on the seesaw of who has the
newest and hottest uP chip in their box -- is history about to repeat itself?
ABOUT THE NEW VELOCE STRATO
A base Strato cabinet has slots for 64 "AVB" boards. Each AVB board handles
40 million gates; which gives a fully loaded Strato cabinet a total capacity
of 2.5 billion gates. This is available now. In 6 months you'll be able to
use a "Strato Link" to connect two cabinets to get 5.0 billion gates. And
within 12 to 18 months it'll be linkable to 15.0 billion gates. Hence their
mktg brag of: "Hey! Our new Veloce Strato platform is ahead of Moore's Law!"
Claims a fully loaded 2.5 B gate cabinet uses 50 KW (22.7 W/Mgate) power.
Claims total "throughput up to 5X (fastest compile-runtime-debug sequence),
time to visibility up to 10X (fastest time to debug), compilation time up
to 3X (with 100% success rate) and co-model bandwidth up to 3X (fastest
virtual co-model solution available)."
(It was unclear if these 5X-10X-3X-3X claims were against the prior flavor
of Veloce 2 boxes or against the current rev of CDNS Palladium boxes.)
My rudimentary understanding is:
- The new Crystal 3 uP is not Boolean based (like Palladium is),
and it's not FPGA based (like Zebu is) -- but some sort of
weird mystery hybrid of the two architectures?
- Claims that this mystery hybrid approach lets Strato have both
"power efficiency" which Palladium lacks, but Zebu has;
plus "visibility" which Zebu lacks, but Palladium has.
- Since Strato is not an FPGA chip, it's roadmap is not tied to
the Xilinx technology roadmap.
- The old Crystal 2 uP was a TSMC 65 nm. I've heard rumors
that the new Crystal 3 uP is a TSMC 28 nm chip. (Unsure.)
I have no idea what GHz either chips run at. I know that
Hitachi designed the old Crystal 2; I have no idea who
designed this new Crystal 3.
- Claims vague "on site at major customers" for Strato, which I'm
guessing is probably Broadcom, ST, and maybe HiSilicon.
The big takeaway is that the new Veloce Strato today can run all 11 flavors
of Veloce Apps with 5 billion gates of capacity -- and it'll be 15 billion
gates in 12 to 18 months. And in a seesaw business where historically the
emulator with newest uP chip wins this new Strato is a direct in-your-face
threat to Lip-bu Tan's Palladium empire.
Have a happy DVcon.
- John Cooley
DeepChip.com Holliston, MA
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