( ESNUG 561 Item 7 ) -------------------------------------------- [06/22/16]
Subject: Cliff Cummings verification-SystemVerilog-UVM DAC'16 Trip Report
NEW SCHOOL RTL SIMULATORS
Cadence RocketSim -- a bunch of Israeli EDA R&D guys have been killing
themselves over the past 9 year to work out the kinks in parallelizing
Verilog simulation into multi-threads on 100's of regular multicore
Intel x86 XEON servers. What they got benchmarked 23X faster vs. VCS,
Incisive, Questa. Does gate and RTL sims. Compiles 1 billion gates
in 2 hours. 4-state-logic for X. Full System Verilog and accelerates
SVAs -- and all this from last year before Lip-Bu bought Rocketick!
Two things changed. The first was Uri Tal and his Israelis came up
with some clever way to get around that "too many events" problem
(which I do not fully comprehend.)
Second is Cadence "Project X". Before RocketSim could only access
VCS/Incisive/Questa through their PLI's -- which was a nasty choke
point. "Project X" is CDNS R&D natively compiling the RocketSim
source C together with the Incisive source C into one GNU C++ object
called "Xcelium" -- thus bypassing that PLI choke point! Now a
50 million gate synthesizable System Verilog RTL design (Little Boy),
Xcelium on 8 core Linux box ran 4X faster than Incisive on a single
core Linux machine. For a 400 million gate design (Fat Man),
Xcelium on 6 cores ran 9.3X faster. That is, the larger the design
with the most activity the testbench stimulus, the better speed-up
Xcelium got! When 400 M gate Fat Man was doing high activity DFT
gate-level simulation it was 30X faster. This 4x-9.3X-30X boost
revitializes the RTL SW market (or at least Incisive's share of it.)
(booth 107) Ask for Uri Tal. Freebie: Denali party tix
- from http://www.deepchip.com/gadfly/gad060416.html
From: [ Cliff Cummings of Sunburst Design ]
Hi, John -
Nice Scoop on those New School RTL Simulators
RocketSim is a new Cadence multi-threaded SystemVerilog simulator that
Cadence acquired right before.
The Rocketick team is led by Uri Tal. The RocketSim simulator divides your
design into many fine-grain, parallel, independent computing elements.
At this DAC, Uri claimed:
2 - 6x for speed improvement for Verilog RTL / SV RTL
5 - 10x for gate-level functional sims
10 - 30x for gate-level DFT (after scan insertion, ATPG - could run
weeks without RocketSim)
Adam Sherer said he could not talk about RocketSim future, but told the
audience to read John Cooley's "highly accurate" description!
Limitations? No SDF backannotated timing yet (working on it). RocketSim
runs RTL simulations with non-accelerated UVM in parallel.
I couldn't find anyone at the Synopsys booth to discuss their Cheetah VCS
equivalent, but that didn't surprise me because it's still 2 years out.
---- ---- ---- ---- ---- ---- ----
Waveform Tools and Debugging Environments
Note: Waveform and debugging tools cost more than a Verilog/SV sim
license, but they run very fast and allow engineers to do cross
analysis and forward/backward movements to debug designs more quickly.
Synopsys acquired Verdi a couple of years back and acquired Atrenta last
year. Both are high quality tools but both Mentor and Cadence mentioned
that their customers have complained of post-acquisition SpyGlass price
increases -- so both Mentor and Cadence were showcasing their SpyGlass-
competing tools at this DAC. CDNS/MENT both claimed they offer better
value with their new SpyGlass-like tools, but I will leave it to engineers
to compare and judge this for themselves.
Synopsys Verdi3 - I tried to get a Verdi update but at the Synopsys booth
I was told that they did not have a Verdi expert at the conference to talk
to me. I was disappointed.
Cadence Indago Visualizer allows users to trace through UVM classes showing
class transaction information in a post processing environment. To quote
the Cadence guys themselves, "Verdi3 cannot do root cause analysis in the
testbench environment." (I'm not sure this is true).
Like most analysis tools, the Indago windows are synchronized & annotated.
This new Indago environment offers a debug analyzer for UVM with licenses
that are a little more expensive than an Incisive license.
The Indago simulation records all messages (UVM_FULL) and then it reduces
"verbosity" with a GUI switch. There is ~10% performance hit for capturing
full "verbosity". I liked the post-process verbosity adjustment switch to
increase or reduce messages based on UVM Verbosity settings.
Mentor Visualizer Debug is advanced debug from the Axiom acquisition a few
years back. (This was years before Badru has his big infamous "C vision".)
The general debug sales strategy is that the big customers would buy a large
number of Verilog or SystemVerilog simulation licenses -- and then far fewer
Visualizer licenses (which do cost more than a simulator license) for the
engineers to do analysis and debug.
Visualizer is advanced debug from the Axiom acquisition a few years back.
Just like the recent Atrenta price raise, Mentor says it's heard customers
complaining the Verdi price has also gone up since the Synopsys/SpringSoft
acquisition -- and is significantly higher than Visualizer. MENT wants to
take advantage of this.
As per the Wilson Studies, engineers spend 2-days per week to do debug.
MENT claims that their Visualizer will cut that debug time.
---- ---- ---- ---- ---- ---- ----
Those Other Spyglass Linting Rivals
Real Intent Ascent Lint beefed up their speed and capacity this year. They
claimed a 500M gate, full chip multi core network processor was lint-checked
with Ascent Lint in 2.5 hours -- and it did not have to break up the design.
Although no benchmarks were shown, they claimed that this was significantly
faster than "competing tools", which I took to be Spyglass.
As with their other Real Intent tools (like CDC) reducing noise in their
reports is a high priority and a big differentiator for them.
Real Intent Ascent IIV is their formal lint tool, with technology that has
been enhanced for the past 15 years. They cited Hogan's Formal Caveat.
"Like a fine wine, formal tools easily take decades to mature.
Buyer beware if you hear an EDA vendor claiming that they
have a 'new breakthough' formal tool."
- Jim Hogan, EDA investor, (ESNUG 558 #5)
New this year is that Real Intent is emphasizing having a database-driven
model to increase capacity -- and they have been standardizing their debug
environment across all of their tools to give a clean environment.
Mentor HDL Designer -- This tool might deserve a better look than I thought.
It's largely marketed as a deep analysis and advanced creation editor, which
has not sparked my interest, but in talking to Mentor-folk, I discovered
that this is Mentor's linting tool as well. As a linting tool HDL Designer
now offers more capabilities than I thought existed in it. As an analysis
and linting tool, it may offer greater value than I thought.
The other two linters, Aldec ALINT and Blue Pearl Analyze RTL operate here
but I didn't have time to see their specific demos this year.
---- ---- ---- ---- ---- ---- ----
BIG HINT: I do regular Verilog and Sysyem Verilog trainings. One of these
lint vendors should create a "lint-lite" tool and give it away so that I
could show it and use it in my training classes. The incentive is to get
engineers hooked on linting tools and perhaps even accustomed to a vendor's
linting environment so that they will upgrade to a full product comfortably
in the future. I am always asked by students if there is an open source
linting tool on the market and the answer is "no".
---- ---- ---- ---- ---- ---- ----
Clock Domain Crossing (CDC) Analysis tools
In 2001, I did my first SNUG paper on Multi-Asynchronous Clock Designs (CDC)
and an updated SNUG paper in 2008 on CDC design and analysis. In 2001, I
noted that there were no tools to help analyze and check CDC designs, but as
of DAC this year there were multiple tools addressing CDC, including:
Mentor Questa Formal CDC, Real Intent Meridian CDC, Ausdia Timevision-CDC,
Excellicon ConDor ("no setup for CDC checking!"), Blue Pearl Advanced CDC,
Aldec ALINT with some CDC checking.
Mentor has been in CDC checking successfully for multiple years.
Real Intent has also been in this space for multiple years and I talked to
my long-time friend Jay Littlefield at Real Intent who re-iterated what
Real Intent is known for with CDC analysis -- it's low noise to bug ratio.
Real Intent's goal is that one design failure should be reported for each
required code change. Real intent has full chip CDC without hierarchical
partitioning and also has Physical CDC checking.
Blue Pearl Software's theme was ease-of-use and that CDC customers have
complained that other tools are hard to use. Their CDC tool is purely
static and it examines RTL code. The tool is marketed as a good static
linting & debug tool. Their CDC view is a domain diagram which shows
clocks, domains with number of synchronized and number of unsynchronized
signals entering each domain. The BP CDC tool also generates SDC for
clock domains.
---- ---- ---- ---- ---- ---- ----
Emulation / Acceleration
The Big 3 EDA vendors continue to push into the emulation and acceleration
space. One of their major pushes is to get engineers to re-code their UVM
testbenches to allow their accelerators to help accelerate testbenches as
well as the RTL code. Larger players in this space include:
Synopsys ZeBu-3 -- I couldn't see their demo this year.
Cadence Paladium Z1 -- (XP was its previous generation). The Cadence folks
mentioned supported features like synthesizable testbenches, Accelerated
VIPs for Paladium, emulation friendly and scales 4M to 9B gates. Each
Paladium is roughly 1/2 billion gates -- where each Palladium user can use
as little as 4M gates.
Mentor Veloce 2 -- I couldn't see their demo this year.
There are other smaller players in here that I didn't have time to see.
---- ---- ---- ---- ---- ---- ----
Badru's Calypto Catapult "vision" vs. Brett's CDNS Stratus HLS
Mentor Calypto Catapult -- I saw that big "vision" post that Badru did on
DeepChip a few weeks before the Austin DAC. Badru outlined a mix of
already existing tools plus some new ideas. He also spoke about a C-based
ecosystem.
"Just like in RTL, it is my hope to also get an IP ecosystem that
brings RTL designers up to speed on HLS. We will need an exchange
of reusable HLS components and IP developed in both un-timed C++
and timed SystemC just like how designers have now for RTL."
- Badru Agarwala of MENT Calypto (ESNUG 560 #5)
Of particular interest I wanted to ask Badru more about his metric-based
C verification concept that he's proposing in his "vision".
But sadly, I couldn't get meet up with Badru. He was very busy. He had a
LOT of customers demanding his time at the MENT DAC booth this year.
Stratus HLS (former Forte tools) -- I spoke with Brett Cline and Sean Dart.
They are very upbeat on how Forte was incorporated into the Cadence family.
They said that despite what Badru said in his "vision", Cadence is not weak
in the High Level Synthesis (HLS) space and continues to add customers.
Stratus HLS is now part of the Digital Solutions flow inside of Cadence
(where it belongs -- it was under verification last year.)
Their new product, Stratus HLS, was released last year and they claim 65% of
the existing Forte customers have already qualified it for use.
Stratus HLS can now see power and congestion -- it can now see digital PnR
congestion points all the way back to the offending C-source code! It lets
the C engineer modify their C-code to make PnR improvements plus it helps
C engineers with design insights. (As far as I know, this insight into the
deep PnR feature only works with Innovus; not with ICC/ICC2/ATOP/Nitro-SoC.)
Stratus HLS claims 24 new significant features. One that caught my eye was
its FPGA Direct -> Xilinx / Altera -- which uses the same C input, but it
produces FPGA-centric output for downstream FPGA synthesis tools. If Brett
wants to write-up the 23 remaining new Strutus HLS features, that's his job,
not mine. :)
Status HLS can handle both datapath & control logic. "It continues to do
well and adoption is growing." But no specific customers names nor counts.
---- ---- ---- ---- ---- ---- ----
FastX - a better VNC replacement
FastX from Starnet Communications is a tool that caught my eye last year at
DAC and is still a tool that interests me.
There are many larger companies that use Exceed remote PC X servers that
should look at this tool for its graphical speed when connected to a server.
FastX is a PC X server that displays EDA tools in the web browser much
faster than a VNC connection.
Of course VNC is free, but VNC tools have to be installed at both ends to
make communication work. The FastX tool is licensed on the server-side, so
anyone who connects does not have to install any tools on their own machine.
I had some troubles installing FastX last year, but I intend to give it
another try this year.
---- ---- ---- ---- ---- ---- ----
Doulos EDA Playground
It is not often that I mention one of my competitors, but Doulos deserves
mention for having acquired the EDAplayground.com web site and making it
available to engineers.
The EDAplayground.com web site includes multiple tools that users can try
including Synopsys VCS and, most recently, Cadence Incisive (Mentor - you
should get Questa on the site). For the user there is a design size limit
(I don't remember exactly what it was) but these tools allow users the
chance to try UVM simulations.
I train a large number of displaced engineers on UVM -- but the problem has
always been that after training these engineers need to practice and there
are no free UVM simulators for engineers to use. EDA Playground offers a
place where these engineers can practice their UVM skills. Kudos to Doulos
for taking on this web site and offering it to displaced engineers. (But
if you already have access to a full UVM simulator where you work, you will
be much better served using your company's full simulation environment.)
---- ---- ---- ---- ---- ---- ----
Cliff Warns Against SVA Training for Engineers
I did a talk at DAC on why 99% of engineers should only take 4-6 hours of
SystemVerilog Assertions training and should use bindfiles (among other
important SVA recommendations). A 2-day SVA training is too much for most
engineers and they lose productivity very quickly.
All of the DAC presentations were taped and they should be on the Mentor
Verification Academy website very soon (perhaps even now). I find this
to be a great service Mentor provides to engineers attending DAC.
---- ---- ---- ---- ---- ---- ----
DAC Austin
DAC at the Austin venue is nice. The food is good and the hotels are much
more affordable in San Francisco. It's also neat to see the more processor
based designers in Texas. DAC will be back in Austin next year and I look
forward to returning in 2017. I am still waiting for a DAC Hawaii !!
- Cliff Cummings
Sunburst Design Provo, UT
---- ---- ---- ---- ---- ---- ----
|
Cliff Cummings has 23 years experience in RTL verification and synthesis training -- and is a founder of SystemVerilog and UVM.
He's won 15 SNUG "Best Papers Awards" out of 41 conference talks he's given since 1993. He looks older than this pic shows.
|
Related Articles:
Cliff Cummings verification-SystemVerilog-UVM DAC'15 Trip Report
---- ---- ---- ---- ---- ---- ----
Join
Index
Next->Item
|
|
