( ESNUG 561 Item 6 ) -------------------------------------------- [06/01/16]
Subject: And the variation part of Amit's 246 engineer SPICE survey...
From: [ Amit Gupta of Solido Design ]
Hi, John,
The last part of my survey of 246 engineers once again (naturally) asked
about the impact of variation on chip design.
DESIGN BEATS OUT MANUFACTURING
Below is the IHS iSuppli snapshot of fab providers per process node:
45/40 nm 32/28 nm 22/20 nm 16/14/10/7 nm
-------- -------- -------- -------------
Intel Intel Intel Intel
Samsung Samsung Samsung Samsung
TSMC TSMC TSMC TSMC
GlobalFoundries GlobalFoundries GlobalFoundries GlobalFoundries
UMC UMC UMC
STmicro STmicro
Toshiba
SMIC
Renesas
IBM
Fujitsu
Notice that the number of foundries went from 11 fabs at 45/40nm down to
just 5 fabs at 16/14/10/7nm. As there are fewer foundries at the smaller
nodes, and because most IDM's are now fabless, IDM product differentiation
no longer comes from clever manufacturing; but instead from clever designs.
For example, while everyone else was still stuck at 28nm, Intel used to
have a big lead because they had 14 nm. This Intel lead evaporated with
TSMC/Samsung/GlobalFoundries now offering 16/14 nm to the whole world.
So in practical terms, now the only way to gain an edge in chip design on
the 4 performance/power/area/yield parameters is by getting a better handle
on how transistor variation specifically impacts these 4 parameters of
your chip.
---- ---- ---- ---- ---- ---- ----
THAT 55nm VARIATION TIPPING POINT
From my survey last year, I effectively predicted that at 55nm is where the
majority of chip designers will start feeling pain from variation. Here's
where I said it visually:
If you look between 65nm and 45nm (at where 55nm would be), that's where
more than 50% of chip designers (the majority) feel that variation issues
start becoming important to them.
Here's the year-over-year of the top TWO drivers of variation design tools:
Notice that although the shapes of the histograms are the same, better PPA
and avoiding respins have been emphasized more. This is caused by two
different herd behaviors going on in chip design now:
These 2 node jumping herds need variation-aware tools for different reasons:
- the 28nm crowd is moving to 16/14/10nm; which is swimming
with variation problems.
- those who jumped into 40/45/55nm, are also now using the
ultra-low power flavors of those nodes and are doing chips like
automotive and IoT; which are swimming with variation problems.
To close competitive PPA designs and to meet schedules (avoid respins), both
herds are using variation-aware design tools.
---- ---- ---- ---- ---- ---- ----
VARIATION HAS BURNED THE MAJORITY OF DESIGNERS
From our new data this year, we've found that 52% of designers have had (at
least one or more) respins or delays caused by a variation problem.
Shown below is the data on designs being done per process node this year
compared to last year.
Having 62% of chip designers now at 55nm (or below), drives home how the
majority of them now have some sort of variation tool need.
Specifically:
- smaller process geometries,
- FinFET and FD-SOI devices, and
- even planar devices, especially when operated at low voltages,
all increase the need for variation-based tools. Also, at these points the
impact of variation is no longer always Gaussian -- many times non-Gaussian
behavior is common, too.
Variation analysis is now a required step in chip signoff.
---- ---- ---- ---- ---- ---- ----
VARIATION-AWARE DESIGN TOOLS WORK
In this survey, 80% of designers used some form of variation-based EDA tool.
And a deeper look into those variation tool users found that:
Which, of course, makes me happy. That's 98% of users seeing some form of
improvement -- with 82% seeing either medium or major improvement.
This is remarkable in how variation-aware design tools gained traction over
the last few years.
The data we are seeing with our customers (we have over 35 including most
Tier 1 semi's, and over 1000 users now) is consistent with this survey data.
In March, we released Solido Variation Designer version 4, which includes
the following enhancements for memory, analog/RF and std cell designers:
- Memory Design: Hierarchical Monte Carlo and enhanced support for
binary and multi-modal distributions
- Analog/RF Design: New Statistical PVT to analyze and verify
worst-case operating conditions
- Standard Cell Design: Batch library verification flow to verify
libraries to 3-sigma and high-sigma
This all results in getting chips with better PPA and yield faster.
- Amit Gupta
Solido DA San Jose, CA
---- ---- ---- ---- ---- ---- ----
Related Articles:
246 engineers surveyed on general SPICE use & SPICE requirements
246 engineers on today's SPICE use vs. their future SPICE use
And the variation part of Amit's 246 engineer SPICE survey...
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