( ESNUG 552 Item 10 ) ------------------------------------------- [10/20/15]

  Editor's Note: Tomorrow Synopsys is holding its first "SpyGlass World"
  after it acquired Atrenta for $214 million earlier this year.  Here's
  what the users saw at Atrenta World'14 six months *before* the buyout.
  It'll be interesting to see what is going to change.  - John

Subject: Getting ready for tomorrow -- Three Atrenta World'14 Trip Reports

From: [ Nonit Kapur of Applied Micro ]

Hi, John,

I attended the Atrenta World user conference and wanted to let your readers
know how it went.  It was held Oct 8, 2014 at the new 49ers Levis stadium
in Santa Clara, CA.

   Nonit's quick report card: A  Best I have experienced in a long time

          Venue and Ambiance: A+ They had all the stadium LED signs and TVs
                                 turned on welcoming us -- really cool).

               Presentations: A  (keynote, TI, 49er guy) to
                              B  (higher than most UGs)

                        Food: A+ for quality, B- for quantity at lunch
                                 (especially vegetarian), A+ for the
                                 reception (that's not the drinks talking)

                   Giveaways: A  choice of snazzy pad-folio for your tablet
                                 or a signed SemiWiki book on fabless
                                 semiconductor industry.

I think most of the slides are available on the Atrenta website.


Opening: Ajoy Bose

Ajoy gave a quick intro with a slide from their VC campaign when they were
founded.  He said they were growing in revenue and customers but didn't say
anything about any acquisitions or IPOs.


Keynote: Karim Arabi, VP of Engineering at Qualcomm

One of the interesting takeaways was that we now have more active SIM cards
than living humans on the planet.  He also reminded us that our mobile
devices are becoming more of a sensor platform as then a computing platform.

Then he got into comparing the human brain to our super computers.  Arabi
said that we (brains) can instantly process millions of parallel tasks at
about 10 steps each -- while super computers can quickly process millions
of steps/lines of code with 10 parallel tasks.  Great food for thought.


User Talk: Shu Chan of Broadcom
           on "CD Demystified for the Masses"

Shu talked about their challenges of multiple tape-outs, multiple IP, little
time to learn tools, and a wide range of CDC issues.  When Broadcom adopted
SpyGlass, they customized the flow to make it easy for novices and experts.

They use an "In-n-Out Burger" simplified menu of rules to keep it simple and
strait forward for new users.  Their experts can turn on more Linting and
CDC rules as they are comfortable.

They want Atrenta to improve GUI, make it easier to move to new versions,
support more Tcl-based constraints.


User Talk: William C Wallace of TI
           on "Things They Never Told You About Chip Design!"

William explained nasty timing glitches, he called Timing Arcs, created by
poor design techniques and synthesis tools -- and how to avoid Timing Arcs
with the proper verification techniques.  At first it seemed very basic,
but then the examples he gave proved to be very valuable.  He showed how
optimizations by the synthesis tools can create big problems.  For each
example William gave specific rules or flows to detect and avoid them. 
hese glitches ranged from asynchronous controls, to preset and clear issues
to asynchronous reset domain crossings to ISO cell usage, and other poor
design practices.  Of course, TI uses SpyGlass to detect these issues
before they cause problems.

William showed how the SpyGlass deployment model allows everyone, regardless
of their expertise, to work quickly through the workflow and find tons of
problems; before the costly synthesis and physical layout processes.  He
said if you're waiting until after simulation or synthesis to analyze power,
DFT, or timing -- you are waiting way to long.  William said you can easily
turn on the checks beyond lint and CDC once you have read the designs into
SpyGlass.  This creates the early feedback to problems that would otherwise
be detected much later in the flow.

William next talked about the difficulty of verifying 3rd party IP and how
management usually "just expects it to work" after they pay for it.  He
explained how the integration of the IP is a big challenge, let alone making
sure the IP was doing what it should be doing -- and whether or not the IP
vendor actually tested it for the way you are using it.  He finished with
some great advice to demand from the IP vendor:

    - Full reusable regression suites
    - Supply IP SW drivers
    - Provide assertions and coverage
    - Detailed co-reviews on each plane post integration
    - Verify your use cases and integration in their test environment
    - Assistance in compliance testing

He recommended the BugScope MARS methodology, which automatically creates
assertions at the IP level to be used at the integration level to pinpoint
integration errors and coverage/bugs.  William said this should be used by
the IP vendors as well as the integration teams.  He finished by warning
people that integrating 3rd party IP was not free -- and in fact was a lot
of work to avoid the risks of having to get a request to debug a customer
failure 2 years down the road.


Marketing: Piyush Sancheti, VP of Atrenta Marketing

No new product announcements at this user group.  Just 5X noise reduction,
10X faster, 6X less memory, and better methodology in the coming releases
later this year.


User Talk: Lluis Paris of TSMC
           on "Bringing Quality & Transparency to the IP Ecosystem"

Fresh off his OIP conference the week before, Luis spoke about the TSMC IP
ecosystem and how they were improving quality and transparency.  He reminded
us that IP usage is growing and that 80-100 IP will be the average for SoCs
later this year.  He touted the TSMC IP portal and how users can see what
they are getting and even compare different IP from this online view.  They
claim to have addressed the quality concern by having all of the TSMC IP on
their TSMC portal run through a rigorous set of SpyGlass rules before it
appears online.


User Talk: S Bandyopadhyay & J Mekkoth both of Cisco
           on "Power Analysis & Structural Connectivity Validation"

These two guys from Cisco talked about how critical power is, even though
they plug into a wall.  It's important because it can keep system costs
down and reduce their fossil fuel footprint.  It's also important for area
and performance.  They showed examples of how, at RTL, you can get various
profiles of activity, gating efficiency and consumption, along with
recommendations for power reduction options.

The second Cisco presenter discussed how they deal with all their memories
(4K of them) and the constant change requests they get for the memory
systems throughout the design phase.  They use the Atrenta MBIST tools to
validate their connections within all of the memory blocks.  They have
runtimes of under 20 min for million gate designs.  They use the tools for
mixed-signal/IO connectivity validation, tie-off/constant propagation,
and validation of trigger-based logic daisy-chain scenarios.


User Talk: Abhinav Balakrishna of Nvidia
           on "Optimizing SpyGlass for Mass Production Use"

Abhinav talked about how they use lint on every FTL block, every night and
report out any issues that have to be resolved the next day.  They worked
with SpyGlass to find huge improvements in their flow.  He reported several
different improvements that gave up to 80-90% reduction in runtime.


Keynote: Jim Hogan, VC at Vista Ventures LLC

Jim provided a bit more color on the topic of IoT.  He discussed 5 trends
that have begun in this realm:

  1. Smartphone penetration and its types of use has only begun: Even
     Karim from Qualcomm noted the mobile phone market is far from
     saturated

  2. The Internet of Things is going to be massively diverse: It's
     going to be way more than wearables and watches

  3. SW app behavior drives HW architecture: This is true if you
     have seen any of the charts that show software costs have
     overtaken the cost of HW

  4. The SW app will run on Open Source components: There is no way
     to cover SW development on a less than $1 per install

  5. Cloud apps will capture most of the value for IoT and mobile
     devices: only place with enough power to any real computing

Jim closed with this slide:

THE ATRENTA WORLD CLOSING:

End of the day Ajoy Bose back onto the stage (wearing a Colin Kaepernick #7
jersey!) to introduce Paraag Marathe, president of the SF 49ers.

Paraag was a great speaker.  Turns out he is the first president in the NFL
of Indian descent.  He climbed the ladder over 15 "seasons" with the team
and spent the last 3 years negotiating contracts and overseeing the building
of the new Levi stadium.  Paraag mentioned that their main focus with the
new stadium was the user experience and how you can see the games from
almost anywhere in the stadium, including standing in line for your beer or
to using the restroom.  They actually have people who monitor and report the
wait times, through their mobile apps, for all the restrooms around the
Levi stadium so you can minimize your time away from the action.

Paraag reported that anyone in the stadium can see replays on their phone
within 2 seconds of the end of each play.  This is better than what coaches
get who must rely on the network feeds!.  Another interesting data point
Paraag mentioned was that during their first preseason game, the fans at
Levi's stadium used twice the bandwidth than the fans at the Super Bowl six
months earlier.  This was despite Levi's having 20K fewer fans!

At the end, he took questions and even answered one about Coach Harbaugh,
who was then in the news about locker room dissention.


OVERALL:

I have to say I enjoyed being able to hear and see the presentations from
the other, less crowded, side of the huge room thanks to the many TVs and
sound system.  I took this flexibility to catchup on some work during the
day while still keeping an ear on what was going on in the presentations.
Many others were doing the same and there was tons of room to stretch out
and relax / work.

William C Wallace from TI won the best presentation award.  The reception
afterwards was top notch with some of the best food I have ever had, let
alone at a football stadium.  All in all, this was a phenomenal event at
a great venue.  I don't know what they will do next year to top this, but
I will look forward to finding out.

    - Nonit Kapur
      Applied Micro                              Sunnyvale, CA

        ----    ----    ----    ----    ----    ----   ----

From: [ Ozair Usmani of Broadcom ]

Hi, John,

I heard that they had over 350 people at the event.  And let me tell you,
Atrenta knows how to do things in style!

For starters, Atrenta World was held in a huge and impressive theater.
(Think 100 yards X 40 yards.)  We were at the balcony level, and as you
looked into the stadium you saw the Atrenta World logo circling the
stadium on the ribbon LED signs.

This is where you usually see the "Let's make some noise!" banners flash up
during a football game.  The next thing worth noting was every single one of
the nearly 100 flat screens all over this room was showing the welcome video
with some infomercial animations.

(Later on, during the presentations, these TVs would show the slides so you
never had to strain to read, even on the way to/from the bathrooms.)
Comparing this other events, I like this new way of doing things.


Ajoy Bose - Intro:

It was challenging to get the crowd away from the views of the stadium and
into the seating area for the presentations, but they managed to fill a big
majority of the seats.

Ajoy started off with a welcome and brief history that included a vintage
slide (circa 2001) he used with the VCs when he was starting the company.

It was interestingly still appropriate for their charter as a company 13
years later.  It was called the prediction problem and showed SpyGlass
filling the "knowledge gap" between the traditional design information that
is available late in the cycle and the requirements to get info as early as
possible to meet your chip schedules.

Ajoy then showed some rah-rah-things-are-great-at-Atrenta slides, but didn't
hint about an IPO or acquisition any time soon.


Dr. Karim Arabi (Qualcomm) - Moore's Law is not Scaling

Karim gave a great talk about mobile computing.  He told us that the reason
our phones will support 4K display isn't because of the screen on the phone,
but because they will be able to drive our TVs.  Qualcomm expects so see
8 billion smartphones shipped in the next 4 years.

He mentioned that Moore's Law is not scaling for costs beyond 28nm due to
node problems and design complexity with no relief in sight.  Kareem then
challenged EDA vendors to provide a 10X gain in productivity, 5X reduction
in power, 50% reduction in area, 1/2 overall design cycle -- and have it
all work with a 10 billion transistor capacity.


Shu Chan (Broadcom) - Demystified CDC for the Masses

Shu talked about their use of SpyGlass CDC and how they have customized a
flow specifically to address their requirements.  They are 10 years into
their use of SpyGlass which started with linting and has grown to include
CDC.  Shu talked about how their flow is easy to use for the Broadcom
newbies while it lets the experts get down to the nitty-gritty details as
needed.  Here is a snippet of the SpyGlass goals Shu's team is using:

    "Redefining and simplifying goals using GuideWare:

       - 2 goals for Lint: One for synthesis, and another for
         synthesis and functional
       - 3 goals for CDC: One for structural and two for functional

Shu did say that they limit their runs to 1-2 million instances and they are
not doing full chip yet.  He specifically mentioned the dashboard reports
and how managers could quickly see the progress of the teams.

According to Broadcom, they have 100+ engineers from many countries who have
taped out more than 10 chips in the last 3 years with their flow and
SpyGlass has been very valuable in finding bugs during this time.


William C Wallace IT- Things They Never Told You About Design

William gave a particularly good talk on how they avoid timing glitches when
your RTL synthesis tool tries to optimize too much.  He gave 5-6 examples of
what happens, and why these Timing Arcs show up after implementation.  For
each one -- I will let the readers see the details on the slides -- he gave
a great explanation on how to detect and avoid these scenarios.

Next he spoke on the EDA flow they use (a bit similar to Shu Chan - above)
and the value in being able to load the RTL design once into a platform like
SpyGlass and then applying the rules for Linting, CDC, Power, and even DFT.

He said you don't have to be an expert to run these tools and every RTL
designer should run RTL checks to avoid headaches in the downstream tools.

Finally, he spoke to the managers and reminded them that IP integration is
not free or even remotely easy.  Just because you pay for it, doesn't mean
it will work without any hiccups or issues.  William said you should ask
lots of questions of the IP vendors and make sure they provide information
about their testing and modes of operation.

At the end, he touched on the MARS methodology with BugScope and how it can
generate a bunch of assertions at the IP level that will help during
integration phase.  I saw this at a kiosk during a break and it appears to
be worthy of a good look.


Piyush Sancheti (Atrenta) - What's New At Atrenta

Piyush spoke before lunch and highlighted a new GUI coming down the road
that helps navigate the design and errors that are reported.

He also mentioned a new power explorer that improves the methodology and
analysis of the Atrenta power offerings.  The big tool news was some major
improvements of 10X faster performance, 5X reduction in noise, and up to
6X lower memory footprint.  This is achieved with some smarter models and
reporting techniques along with some more formal technology.


Lluis Paris (TSMC) - Bringing Quality & Transparency to the IP Ecosystem

After a nice lunch break and demos at the kiosks around the room, Lluis
talked about their flow that uses SpyGlass to "clean" all the IP that goes
up on the TSMC online portal.  He said they use a lot of the documentation
and metrics that gets created to give the TSMC online users a view into the
quality and capabilities of the IP.  This was interesting to hear from a
company that claims to have 7600 IP titles from 0.35u to 16FF, and 70%
market share.

S. Bandyopadhyay and J. Mekkoth (Cisco) -
    Power Analysis & Structural Connectivity Validation of an SoC

Two co-presenters from Cisco talked about the problems related to:

  - their design groups being all over the world,
  - having multi-million gate blocks to integrate, and reuse
    across designs, and
  - the 3rd party IP they get to use.

Even though Cisco systems are plugged in (not battery based), they are still
under pressure to reduce power while enforcing a common methodology across
their teams.

They walked through a detailed example of how they were able to profile the
full chip activity, memory access rates, clock gating efficiency, and
sequential/combinatorial activity with their RTL.  This allowed them to
estimate power consumption early and take steps to reduce power before RTL
synthesis.  The results provided better correlation with silicon power;
while allowing them to optimize the system and build the power data into
their thermal simulations to avoid worse-casing or over-margining the chips.

Next, Cisco talked about memory BIST validation with the problems of having
1000s of physical memory units within 100's of design blocks and constantly
changing memory requirements.  They needed to have a standard methodology to
address all of these challenges with PrimeTime.  With the SpyGlass tools,
they were able to implement this MBIST validation with common constraints
for all design blocks.  The results were seen in less than 20 minutes of
runtime for million gate blocks and they were able to correct issues such
as pipelining on the connection path which violates handshake requirements,
wrong tie-off values during incremental memory changes, and missing memory
connectivity at different levels of hierarchy.


Jim Hogan (Vista Ventures) - What Does IoT Mean to Me?

Jim told a great story of how he actually used several IoT monitors to track
his granddaughter's health before and after birth, while also tracking his
aging father-in-law who, on occasion, has forgotten to turn on the heat in
his home.  Some of this information also goes to the doctors, while some of
the information can be viewed on his phone.  He even has the option to turn
on the heat for his father-in-law, several states away, with his phone if
the older gentleman forgets!  If there was any doubt before, the IoT era
is already here, at least for Jim.


Abhinav Balakrishna (Nvidia) - Optimizing SpyGlass for Mass Production Use

Abhinav talked about how Nvidia used the linting tool in their regression
runs every night for their designs and how it catches "killer" bugs and
mismatches between synthesis and simulation.  They run nightly regressions
on all design check-ins and comprehensive full chip regressions 2X a week.
They reported some serious runtime improvements:

    1) 70% by turning off the non-important 'info' level checks,
    2) another 33% by eliminating redundant rules, and
    3) another 40% drop by optimizing the waivers.

  Design A: Original - 4582 seconds (1 hr 16 min)
  Design A: With All Optimizations - 510 Seconds (8.5 min)
            an 89% reduction in runtime

Net-net was runtimes decreasing by 80% - 90%.  I suspect anyone who saw this
presentation quickly called their AEs out to look at their own flow and help
them optimize to realize these kind of improvements.


Paraag Marathe, president of the 49ers

Paraag gave an awesome talk about how he negotiated NFL player contracts and
helped spearhead the new Levi stadium.  He talked about their focus on the
user experience and some of the great technology they have incorporated at
the stadium.

You can get any food delivered to anywhere in the Levi stadium seats in under
8 minutes (their target).  You can even look up on their App how long the
different restroom lines are.


Atrenta Areas of Improvement:

Different companies gave some feedback to Atrenta.  It ranged from reducing
the effort to move to new releases, to reducing the number of rules/goals
they provide with the tool.

Other companies called for smarter tool reporting of violations, especially
across versions and waiver audit reports to avoid blanket waivers.

During the breaks, there were 5-6 different kiosk-type stations where you
could hear from the marketing people about the latest stuff from their
various products.  They had slides and demos of their latest versions
highlighting the new wiz-bang stuff.  I saw quite a few groups of people
taking it in.

The evening reception was great, too, and I'm waiting to see what they do
at next year's event.

    - Ozair Usmani
      Broadcom                                   Santa Clara, CA

        ----    ----    ----    ----    ----    ----   ----

From: [ William C Wallace of Texas Instruments ]

Hi, John,

I attended the Atrenta World conference on October 8th last year (2014) in
Silicon Valley.

The Levi Stadium Club was a nice venue.  They spared no expense to make us
feel welcome plus a great first impression to ATRN users.  (food and drinks)

I gave a 3 part presentation and got best presentation award along with very
nice feedback from several attendees.  But that's not why I am writing.  I
wanted to share with your DeepChip readers my conference notes for my
colleagues who couldn't make it to AW.


AJOY'S KNOWLEDGE GAP

Ajoy presented a slide from 13 years ago that he used with the VCs when he
was collecting money for the company.  It still rings true today.

The concept is that over time you build up and collect design information.
The available information is slow in developing, especially early, but
eventually gets pretty close to where you need / want it.  The problem is
that you have to make decisions much earlier than when this information
is traditionally available. This points to the need for a tool to bridge
the knowledge gap or to build the knowledge more quickly in an efficient
and affordable way.

What makes this even more apropos today is the fact that there is TONS of
data collected, and a lack of "local" knowledge thanks to 3rd party IP
and smaller teams (that don't always have the expertise they wish they had).

I hope all the engineering managers stop and think about this one, because
they seem to think that once you pay for the IP, there is no additional
cost.  Atrenta seems well positioned in this space and capitalizing on it
based on his next few slides about business being good for them.


THE TALKS:

Dr. Karim Arabi, Qualcomm VP of R&D

Their next SoC design is pushing the envelope HARD in ALL areas, and there
is no looking back for them.  The target is 10nm and they are confident
they can make it work.

I really liked his discussion about neural processors (NPUs) as a focus on
lower power computing.  He had some great analogies between the human brain
and our super computers.

Qualcomm's challenges

  - Verification of HW + SW, a 2^N issue
  - Too many chip designers are required -- 1000's he said
  - EDA Companies need provide solutions to increase productivity
  - DDR bottleneck
  - Power / Heat

Karim showed a slide that indicated that the processing power of mobile
devices will surpass desktop computing in 2015.

I got a chance with the microphone when he was discussing 3D VLSI, and asked
about heat.  He said they do not stack / align the hot spots.

On 3rd Party IP

  - They do FULL verification of the IP when they get if from the vendor.
  - There is no free lunch (even when you pay for it)


Jim Hogan, VC, keynote

  - Jim said there would be fewer SoC designs in the future, and that more
    focus would be on SW on the device.  He suggested that Intel has 7K
    SW developers, and Qualcomm has a ratio of 2 to 1 (SW/HW)
  - IoT will require very cheap silicon, while the money will be made in
    the apps/SW.
  - Cloud has very high growth margins; driver for the IoT movement
  - Complete SW verification is almost impossible, that's why we have
    security/privacy problems.


Lluis Paris, TSMC, keynote

  - He claimed that technology is not the issue, TSMC can do 5nm.
  - The issue is affordability (costs) of the lower nodes not
    scaling to Moore's Law.
  - TSMC has 70% market share, but 0% in the memory space
  - TSMC providing more and more IP data (CPU, Serdes, PCI etc.)
    Fmax, Vol, Yield, etc.


Atrenta Status according to Ajoy and Piyush:

  - All big companies use SpyGlass.  ATRN had strong growth in 2013/2014.
    ATRN has 384 customers now.
  - Ajoy said he did not know the industry had so many chip folks.
    One new customer was a major refrigerator company doing a new
    ASIC in China.
  - SpyGlass Power: Large base of users, gaining market share
  - BugScope is having a strong adoption as customers see the value
  - In theory, rev 5.4 will finally have solid / unified TCL

Plus they are having some issues trying to maintain backward compatibility.


WHAT THE ATRENTA USERS SAID:

  - Cisco uses structural verification for DFT BIST verification, good
    presentation on this
  - SpyGlass checks are a gate (requirement) for RTL check-in.  Most
    companies run nightly regressions on all designs
  - Improved SpyGlass run times, optimize rule set and waivers.
    NVidia got 80% reduction in CDC.
  - Most users have library CDC widgets, like async FIFO's.
  - SoC-level RTL verification is very challenging (we knew this)
    but possible with Atrenta's "smart" abstracted models (we
    should look into this).

Plus their CDC hybrid (with formal technology) is better now according to
one user.

    - William C Wallace
      Texas Instruments                          Dallas, TX

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   !!!     "It's not a BUG,
  /o o\  /  it's a FEATURE!"
 (  >  )
  \ - / 
  _] [_     (jcooley 1991)