( ESNUG 552 Item 3 ) -------------------------------------------- [10/08/15]
Subject: Real Intent DAC'15 survey on CDC bugs, X propagation, constraints
DAC'12 "When is your next design start?"
0-3 months : ############################################ (53%)
3-6 months : ######################## (29%)
6-12 months : ############### (18%)
My reaction to seeing over half of the future design starts occurring in the
next 3 months leads me to think design activity is not slowing down, but
in fact is remaining strong despite any uncertainty there might be in the
economy.
- from http://www.deepchip.com/items/dac12-06.html
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From: [ Graham Bell of Real Intent ]
Hi, John,
We redid our 2012 DAC survey this year at the 2015 DAC in San Francisco and
here are the results. We had 201 surveys turned in at our DAC booth.
DAC'15 "When is your next design start?"
0-3 months : ########################################### (52%)
3-6 months : ###################### (26%)
6-12 months : ################## (22%)
These numbers are very similar to what was reported in 2012 on DeepChip.
With half of the future design starts occurring in the next 3 months, this
leads me to think design activity is remaining strong despite any EDA user
consolidation we might have seen with the big mergers of various chip
companies, and the slowing of the Chinese economy.
However, the latest IC forecast from Gartner has 2015 growth falling from
5.4% at the beginning of 2015 down to 2.2% in July.
DAC'15 "How many clock domains do you expect it will have?"
under 50 : ################################################ (58%)
50-100 : ##################### (25%)
100-500 : ######### (11%)
over 500 : ##### (6%)
We asked this to find how many asynchronous clocks need to be analyzed by a
CDC verification tool. When we see designs with over 100 clock domains
they are typically mobile devices that use aggressive low-power goals with
multiple clock schemes to hit their power target. Designs with under 50
clock domains are often block-level designs such as hard IP, or those for
commodity consumer electronic products.
Since 2012 we have seen a 10% increase in the number of designs with more
than 50 clock domains, so system complexity continues to grow. What is
interesting is that Harry Foster's 2014 Wilson Group study reports much
smaller numbers. We think our numbers are higher since respondents may be
counting a mix of synchronous and asynchronous clocks in their designs.
"Have you seen CDC bugs resulted in late ECOs?"
Yes : ############################### (61%)
No : ################## (39%)
"Is CDC verification a sign-off criterion?"
Yes : #################################### (72%)
No : ############# (28%)
These numbers match those reported in 2012. Most designers have been burned
somehow by clock-domain crossing (CDC) bugs -- and even more now treat CDC
verification as a sign-off issue. What are the other 28% doing? Some chip
design teams tell us that their methodology is immune to CDC issues, or that
their number of clock-domains is small because they are designing IP or
other small blocks. But we think this isn't typical for fabless semi design
teams that are combining heterogeneous IP from different vendors.
"What verification technologies are you looking to adopt or change?"
CDC : ############# (25%)
automatic
formal checks : ########## (19%)
design constraint
analysis : ########### (21%)
X-propagation
analysis : ###### (12%)
lint : ############ (23%)
These 2015 adopt/change responses are fairly close to the 2012 adopt/change
responses. That is, chip designers are looking across all 5 technologies
vs. favoring just one individual tech.
"What issues have you encountered with your current CDC or Lint tool?"
performance : #################### (40%)
noisy reports : ######## (15%)
capacity : ########## (19%)
waivers : ############# (26%)
We were not surprised tool performance is a strong #1 issues for CDC. We
often meet designers who are struggling with their existing tool. What is
surprising is the Waivers response. Waivers are a dangerous design method
in sign-off since they disable the rules and good practices based on the
designer's knowledge or intuition (right or wrong) that the circuit in
question is good. Unfortunately it is easy to get bitten by special cases
and exceptions.
"What 'X' (unknown) issues affect your designs?"
X-Optimism : ################### (38%)
X-Pessimism : ################ (31%)
low power techniques : ########## (20%)
must Reset all flops : ###### (11%)
For several years we have had a tool for uncovering and mitigating unknowns
(X's) in design and we continue to survey awareness of this issue. The X
problem is two part: X-optimism in your RTL can mask functional bugs while
X-pessimism in simulation causes unnecessary X's at the netlist level.
There is less engineering awareness of possible X problems with the use of
low-power design techniques and the reset of hardware between power modes.
We expect this to be a growing verification challenge.
"For SDC timing exceptions and constraints management,
what 'pain points' exist for you?"
constraints checking : ################ (32%)
exception verification : ######### (17%)
constraints creation : ########## (21%)
SDC consistency : ############### (30%)
We weren't surprised that "constraints checking" was the main problem. With
the widespread use of IP and hierarchical design styles, it's getting more
and more difficult for designers to know that all constraints are consistent
across his design hierarchy. And "constraint creation" for the chips has
become more of a headache; which drives the need for a usable SDC generator.
We were a little surprised at the low number for "exception verification".
Customers have told us incorrect exceptions have caused them costly respins.
"Does your current Lint have limited usage because
of speed, capacity or poor-reporting?"
Yes : ########################## (51%)
No : ######################### (49%)
It is surprising to me that a mature tool like an RTL linter -- they've been
around for close to 20 years now -- still lacks levels of satisfaction. This
is good new for Real Intent. It means there's opportunity there.
"When doing full-chip verification are you still
finding block-level bugs?"
Yes : ##################################### (74%)
No : ############# (26%)
"Are you using automatic formal analysis currently?"
Yes : ################################### (70%)
No : ############### (30%)
We wanted to draw a connection between block-level bugs and the need to use
more formal verification. Unfortunately, our survey shows that even though
formal analysis is being used, block-level bugs are still happening despite
the fact that formal tools are ideal for cleaning block-level bugs. This
suggests more work is needed to push adoption of formal tools and make them
easier to use.
---- ---- ---- ---- ---- ---- ----
WHY I'M STOKED
This survey showed that CDC analysis is now a sign-off criterion for the
majority (72%) of designs, and that better verification is needed (61%) to
stop CDC bugs causing late ECOs. Compared to the 2012 results, we see
greater complexity in the number of clock domains that need to be analyzed.
I'm happy to let you know that Meridian CDC from Real Intent is still the
answer. Its structural/functional analysis ensures that signal crossing
asynchronous clock domains are received reliably in designs in 500M gate
designs that have more than 100+ clocks.
The survey also highlights the need for a better RTL lint tool -- one with
better performance and an easy find-and-fix use model -- such as our very
own Real Intent's Ascent Lint. (I had to do some pitches here, John!)
Finally, we're happy to see designers' concerns about both X-optimism in
their RTL and X-pessimism in their gate-level netlists have been addressed
by tools now available in the market such as our Ascent XV. :)
- Graham Bell
Real Intent, Inc. Sunnyvale, CA
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