( ESNUG 551 Item 3 ) -------------------------------------------- [06/02/15]
Subject: And the variation part of Amit's 317 engineer SPICE survey...
> ...and that this will consequently cause more SPICE evals to happen.
>
> "Does your group plan to evaluate/add any new
> SPICE simulators within the next 12 months?"
>
> Yes: :############# 26%
> No: :##################################### 74%
>
> This comes from the new 16/14/10 nm nodes needing lots of SPICE work,
> plus SNPS acquiring Magma, MENT acquiring BDA (and Tanner), plus the
> CDNS/BDA lawsuit being settled plus the new ultra-low power nodes at
> 45/28/16 nm; all make for a perfect storm of increased SPICE demand
> added to a legal unfettering of the SPICE vendors.
>
> - from http://www.deepchip.com/items/0551-01.html
From: [ Amit Gupta of Solido Design ]
Hi, John,
And the last part of this survey of 317 engineers asked them about a topic
close to home for us at Solido -- how variation impacts which EDA tools they
used and how they designed with them.
MANUFACTURING LOSES TO DESIGN
Below is a 2014 IHS iSuppli snapshot of fab providers per process node:
45/40 nm 32/28 nm 22/20 nm 16/14 nm
-------- -------- -------- --------
SMIC UMC TSMC TSMC
UMC TSMC GlobalFoundries GlobalFoundries
TSMC GlobalFoundries Intel Intel
GlobalFoundries STMicro Samsung Samsung
Renesas Intel
IBM Samsung
Fujitsu
Toshiba
STMicro
Intel
Samsung
Notice that at 45/40 nm there are 11 fabs. At 16/14 nm only 4 fabs.
As there are fewer foundries at the smaller nodes, and because most IDM's
are now fabless, IDM product differentiation no longer comes from clever
manufacturing -- but instead from clever designs. For example, Intel used
to have a big lead because they had 14 nm -- while everyone else was still
stuck in 28 nm. This lead is evaporating with TSMC/Samsung/GlobalFoudries
now offering 16/14 nm to the whole world. So now the only way to gain an
edge on performance/power/area/yield is by getting a better handle on how
transistor variation specifically impacts these 4 parameters of your chip.
Our survey data confirmed this with reducing over-design for better PPA and
reducing under-design for better yield, and avoiding respins as being their
topmost drivers (each ~40%) for using variation-aware design tools.
---- ---- ---- ---- ---- ---- ----
VARIATION-AWARE DESIGN TOOL USE GROWS
What we liked was while 28% were using variation-aware tools now, within the
next 12 months that's going to grow to 66%!
This 12 month growth is no surprise because of the shifts to 16/14/10 nm for
the bulk of chip designs within the next 18 months.
"At what node is your group currently designing in?"
>90nm : :################## 18%
65/90nm : :########################## 26%
40/45/55nm : :############## 14%
28/32/35nm : :######################## 24%
14/16/20nm : :################## 18%
By the time you get to the nodes involving FinFETs (everything below 20 nm)
virtually everyone said that variation-aware design was necessary. As time
goes on, that shift to the lower nm nodes will only grow.
WHAT VARIATION TOOLS NEED
We expected SPICE accuracy and the integration of SPICE with simulation
clusters (and foundry PDK's) to rank highly with the engineers. "Why bother
with a PVT analysis that doesn't match final silicon?"
What was interesting on this one particular survey question was how the mass
of engineers rated "Speed Gains - SPICE Sim Reductions" as a "must have"
for their custom IC design tools.
It's important to realize what this means. "Speed Gains" is simple. They
want faster SPICE runs. That's obvious. Let's say to do all PVT corners on
their full custom digital transceiver takes 5 hours running on 200 Spectre
licenses. If Spectre speeds up 20%, that's now only 4 hours. Simple.
"SPICE Sim Reductions" is similar. The engineers want to run fewer SPICE
runs. That's clear, too. If you can do the same PVT analysis with only
100 Spectre licenses, that saves money, too.
But putting the two together is what the engineers really want. Let's say
you want to find the 6-sigma "read" current of a bitcell. (6 sigma is
1 failure in a billion.) Technically that means you'd have to do 1 billion
SPICE runs! But if you can do 6-sigma Monte Carlo with some exceptionally
clever sampling, that can be intelligently cut down to 5,000 SPICE runs;
an easily done task which saves both run times and licenses.
---- ---- ---- ---- ---- ---- ----
VERIFIABILITY
And our survey found that 31% wanted verifiability of results. They want
to know if their variation SPICE run is converging or not. And then did the
run output an inaccurate result?
For example, when SPICE fails, the user can tell because KCL or KVL are
violated. Our customers like that we have convergence plots showing if
their results were accurate and trustworthy. Without such plots, the user
risks getting results that over-/under- estimates yield or performance.
- Amit Gupta
Solido DA Saskatoon, Canada
---- ---- ---- ---- ---- ---- ----
Related Articles:
317 engineers surveyed on general SPICE use & SPICE requirements
317 engineers on today's SPICE use vs. their future SPICE use
And the variation part of Amit's 317 engineer SPICE survey...
---- ---- ---- ---- ---- ---- ----
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