( ESNUG 549 Item 3 ) -------------------------------------------- [04/23/15]
Subject: Hogan cautions Frank missed the segway in 2 emulation use modes
> ... the main advantage of processor-based emulation is fast turnaround
> time for bring-up, which makes it ideal for the project phase in which
> RTL is not quite yet mature. In addition it allows multi-user access
> and excellent hardware debug insight in the context of real software
> that can be executed at MHz speeds, resulting in very efficient HW/SW
> debug cycles. Standard software debuggers can be attached using JTAG
> adaptors or virtual connections.
>
> ... FPGA-based emulators are more applicable for later project stages
> in which RTL has become more mature.
>
> - Frank Schirrmeister
> http://www.deepchip.com/items/0532-04.html
From: [ Jim Hogan of Vista Ventures LLC ]
Hi, John,
Frank is correct when he says that processor-based emulators (like his whole
family of Palladium boxes) have good turnaround time for a fast bring-up.
And that higher intrinsic speed FPGA-based emulation works well for mature
designs. But Frank failed to address how users bridge that transition.
---- ---- ---- ---- ---- ---- ----
EARLY VS. STABLE EMULATION USE
The need for a specific emulator type -- processor-based emulation (PBE) or
FPGA-based emulation (FBE) -- varies according to your project's phase.
Processor-based emulaton: Cadence Palladium
FPGA-based emulation: Mentor Veloce, Synopsys Zebu
Early: RTL exploration and verification
You need high visibility here, as you are exploring architectures
and trying new ideas. This in the phase where RTL is still fresh,
less mature and less stable.
Profiling transactors in terms of bandwidth and transaction rate
in the system is a main task. Debug demands are most critical.
How fast can you get the design compiled and into debug? What's
the values of the XYZ bus from the 5,234 to 5,238 cycles?
Bugs are raw and obvious at this point. 2 + 2 == 22 ???
The early stage has only dozens of HW intensive designers using
emulation -- who are slowly outnumbered by verification engineers
developing their first tests.
Processor-based verification is heavily used in this phase, given
its fast bring up time, its debug abilities, and its ability to
handle design complexities.
Stable: Firmware, OS boot, drivers, final SW apps
If the SoC still has bugs, they're be subtle and hard to find.
Many of the verification tasks that were normally done when the
first silicon comes back are now done pre-silicon in emulation.
A few HW designers are around, but it's verification engineers
running full regression suites to catch those elusive bugs who
will take up most of the bug hunting emulation cycles.
Because the SoC is stable, this is where hundreds of SW driver
and SW app developers use emulation to create the final product
that is being delivered to a market.
SW developers often mix execution engines (e.g. virtual platform
and emulation, plus traditional in-circuit emulation.) For pure
SW driver work, real software debug environments are created.
You need lots of emulation capacity here; some for regressions,
but mostly for the hundreds of SW apps developers.
Both FPGA-based and processor-based emulation play here. Since
far less HW debug is needed, FPGA based prototyping becomes very
attractive due to its lower price/gate.
Bottom line it is not an easy call, because most companies cannot afford to
have a mix of PBE and FBE emulators systems in parallel. Additionally,
Synopsys ZeBu and Mentor Veloce, though both FPGA-based, have a number of
distinct differences between them.
It has become a balancing act.
Debug is a must, hence the attractiveness of processor-based emulation as it
is best at bring-up and also scales to the regression -- albeit at somewhat
higher cost. But how many regressions will one have? Or will FPGA based
prototyping finally become capable enough to fix its slow early debug and
weak internal access problems?
- Jim Hogan
Vista Ventures, LLC Los Gatos, CA
---- ---- ---- ---- ---- ---- ----
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