( ESNUG 546 Item 3 ) -------------------------------------------- [01/15/15]
Subject: Wally Rhines and 23 other engineers on "free" MENT cell-aware ATPG
> One rule of thumb I've heard is a std cell lib verification takes a team
> of 3 engineers ~4 weeks to do. That's 3 engineers x 20 days x 8 hours
> which is 480 man-hours. 5 libs is 2,400 man-hours. Assume 1 engineering
> man-hour costs $100. 5 libs is therefore 2,400 x $100 == $240,000.
>
> Now assume you can get some economies by doing 5 libs at once, you should
> be able to cut this cost in 1/2, so, after all the estimations:
>
> Wally's so-called "free" cell-aware ATPG actually costs $120 K!
>
> Is this bad? Not really. This is useful for chips with a long-cycle-life
> like automotive electronics that have to run for 10+ years, or for
> critical medical applications like implanted heart pacemakers.
>
> But it's not free.
>
> - Luis Basto, DFT consultant Austin, TX
> http://www.deepchip.com/items/0538-12.html
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From: [ Wally Rhines of Mentor ]
Hi, John,
First off let me say thank you to Luis Basto! I do a lot of keynotes
and I can't tell you how happy it makes me to have someone pay this
much attention. I really enjoyed his summary.
As for the "free" comment, all I can say is that you are correct;
there is no free lunch. Although Mentor isn't charging extra for
TestKompress to generate cell-aware test patterns, there is a cost to
generate the fault models needed for use in ATPG.
While I can't verify your $120 K estimate, keep in mind that the
library generation is a one-time cost. Once you generate your
models, you can use them for all future designs that utilize that
technology library.
Long term our hope is that the std cell lib IP providers will supply
these views as part of their standard cell library package. While
we're not there yet, this would certainly reduce the burden and
cost to the end user.
In the meantime, we also have a turnkey Mentor consulting offering
that can generate cell-aware fault models for our customers. While
this is not a free service, it's much less than $120 K.
Thanks again, Luis, for a really great write up.
- Wally Rhines
Mentor Graphics Corp. Wilsonville, OR
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There is no free lunch.
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What is the American saying? No free lunch!
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Please thank Luis for his estimates. I used it to teach my cheap
ass management about how much it costs to qualify a lib. They
think it's make-work and wasted engineering time.
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Luis forgot to add in compute farm time and costs. It's not free.
---- ---- ---- ---- ---- ---- ----
If you're extracting LDE wouldn't each cell placement border be
unique? That means you can't extract for ~300 cells, but instead
you have to extract for each specific instance, no?
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Luis wrote:
"SPICE simulations are done on PVT-RC corners,
so 5 x 3 x 3 x 6 == 270 corners."
Could he please break out exactly what 5 x 3 x 3 x 6 is?
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Nothing worthwile in life is free.
---- ---- ---- ---- ---- ---- ----
No free lunch.
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I like Wally's talks. Even when he's trying to sell you something
he's not trying to sell you something.
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I was at that SWDFT conference in Austin. It was co-located with DAC.
Wally's talk was the best talk on test for that whole week.
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Luis' scale-of-economy is off. If 1 lib takes X work. 5 libs does
not take 5X nor 2.5X but closer to 1.5X if you have a team that
can script well. $120 K is wrong. Should be $72 K for 5 libs.
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LSSD! Talk about olde memories. I did LSSD test when I was young.
---- ---- ---- ---- ---- ---- ----
BEST WALLY QUOTE SO FAR:
"A single EDA vendor tool flow doesn't make sense."
Try telling our local Synopsys sales guys this.
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John Waicukauski is the great grand pappy of all modern test.
It's good to see Wally recognizing him for this achievement.
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No free lunch.
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The only reason why Synopsys owned 1/2 of scan insertion in 2000
was because of Design Compiler dominance then. In those days scan
insertion was a natural part of synthesis.
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I would kill for the golden years when "stuck-at" and transition
faults were the only thing we had to worry about. All this extra
PD crap for test sux.
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I forgot when Wally's sales guy tried to sell us TestKompress for
$1 million a seat. We thought it was a practical joke at first.
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FinFET 16/14 nm is yield nightmare for everyone but Intel right now.
At 10 nm we're all fucked.
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Wally estimates that "cell-aware" ATPG will increase the total volume
of test vectors to 50% or more.
NOT GOOD! WE CAN'T HANDLE 50% MORE VECTORS!
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I'd be interesting in hearing what Wally thinks about using FD-SOI
instead of FinFET. Will FD-SOI use significantly less test?
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A test engineer complaining about too many long-winded standards.
That bureaucracy is why I stayed in design. No, thank you.
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Does Cadence still do cell-aware ATPG? Why did they abandon it?
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Related Articles:
Test consultant irked at Wally's misleading cell-aware DFT launch
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