( ESNUG 540 Item 6 ) -------------------------------------------- [05/16/14]
Subject: Trent's 12 tips on transistor and full custom low voltage design
> In this ESNUG post I wish to examine how the recent trend of dropping the
> on-chip voltage (VDD) -- to cut power -- ripples throughout every stage
> of chip design. Simply put:
>
> Power == (Voltage^2) / Resistance
>
> That is, as a chip's VDD drops linearly, power use drops geometrically.
>
> What follows are the nuances of how dropping to ultra-low voltages (to
> save on power, and while still maintaining performance over a range of
> temperatures) impacts how our chips are designed.
>
> - Jim Hogan
> Vista Ventures, LLC Los Gatos, CA
From: [ Trent McConaghy of Solido ]
Hi, John,
To minimize energy, you don't just lower voltage -- but also resistance, and
even time too. For example:
- Resistance component -- minimize active (or dynamic) power
consumption and static power consumption (leakage).
- Time component -- low-as-possible power for each given
use mode (e.g. standby)
Such optimizations in resistance and time also involve significant analog
thinking; but the focus of this article is on low voltage. Let's proceed!
---- ---- ---- ---- ---- ---- ----
HOW TO DESIGN ULTRA-LOW VOLTAGE ANALOG/RF/CUSTOM CHIPS
These complementary high-level approaches are a path towards ultra-low
voltage custom ICs:
There are three basic high-level ways to design low voltage custom IC's:
1. Use clever device/topology/architecture design techniques
for low voltage
2. Use clever manufacturing flows specifically optimized
for low voltage
3. Measure the relationship between energy/performance/yield;
and design for it
The first approach (clever topologies) is incredibly important, what one
traditionally thinks of as "low voltage" design practice, and where you see
many articles about low voltage at leading conferences and journals.
But the other two approaches (manufacturing & measuring) are complementary,
and necessary to get "low voltage" in industrial use.
The second approach (manufacturing) can be put in place by design managers,
process groups, and testing groups. The third approach (measuring) is
perhaps "obvious" top chip designers, but this is where EDA tools can play
a significant role.
We now examine each of these high level approaches in turn.
---- ---- ---- ---- ---- ---- ----
1. CLEVER LOW VOLTAGE DEVICE/TOPOLOGY/ARCHITECTURE TRICKS
Ultra-low voltage circuit design has been under active research for quite a
number of years. For example, in work stretching back to the early 2000's,
Prof. Peter Kinget and his team at Columbia have demonstrated 0.5 to 0.6 V
analog/RF design on everything from simple OTA's to full RF front-ends.
Here are some approaches, with the related academic papers referenced, that
directly address low-voltage design:
- In analog, exploit full device characteristics. This includes
using reverse short-channel effect (RSCE) and body-biasing
techniques. The general aim is to have your MOS devices in
the weak inversion operation, with V_DS > 0.10 to 0.15 V (with
overdrive voltage < or = 0.2 V).
- Simplify analog topologies, aiming for rail-to-rail operation.
Low energy, and low voltage, involves compromise with performance.
Basically, one aims for a target performance and has zero
performance margin above that. And zero voltage margin, i.e.
rail-to-rail operation. This means removing cascode stacking,
local common-mode feedback (LCMFB) structures, common-mode
feedforward (CMFF) structures, voltage boosting, and more.
- Tweak analog/RF/MS architectures. For example, removing switches
in your signal path, and designing RF front ends with current-mode
operation.
- Cell-level and block-level custom digital techniques include:
reducing voltage adaptively (dynamic voltage scaling), slowing
down subcircuits when possible (dynamic frequency scaling), and
putting unused subcircuits into the standby, sleep, or power-off
states (static leakage management).
- In analog/RF/MS architectures, leverage digital techniques, and
therefore digital low-voltage techniques. Whereas transistors for
analog functionality tend to be big, transistors for digital logic
and memory are tiny and cheap, so we can "waste" logic and memory
transistors in the effort to improve analog performance /
linearity / etc. It's masses of tiny worker ants serving a (few)
big queen bees. Examples:
- Digital assistance to self-calibrate an RF front-end
(Feng et al, ISSSC 2010).
- Self-adjusting amplifier, which digitally stores how
much to compensate, and via a DAC converts that to an
analog trim voltage (Yu et al, JSSC 1994)
- Combine a slow-but-accurate ADC (sigma-delta) with a
fast-but-inaccurate ADC (pipelined) by way of digital
calibration (Chiu et al, TCASI 2004). Then leverage
digital power-saving techniques.
- In digital circuits, leverage analog techniques. Examples:
- Sub-threshold computing. That is, use sub-threshold
leakage as your operating current. Sub-threshold gates
have very good voltage transfer characteristics (I_DS
response to V_GS) and capacitance profiles. However,
they're limited to a few hundred Mhz, and are highly
susceptible to variation effects.
- Clock distribution draws a large portion of power. There
are two philosophies to address this:
1. keep the clock, but make it cheaper; or
2. toss the clock.
For the former (keep), there are tricks to synchronize PLLs
or DLLs in clock distribution networks, such as partitioning
the chip into different zones and giving each zone one PLL
with phase detectors to neighboring zones (Gutnik, JSSC 2000).
For the latter (toss), this means going asynchronous when
possible. Asynchronous may bring massive order-of-magnitude
power reductions. The lack of familiarity is probably its
greatest adoption challenge.
- For digital cells, use low power / low leakage static gates. One
example is the Schmitt-triggered-inverter-based-gate structure
(Lotze, ISSCC 2011), which actively suppresses leakage current by
way of a virtual supply and virtual ground created by pull-up and
pull-down networks. This can be effective in combination with
asynchronous design.
---- ---- ---- ---- ---- ---- ----
2. CLEVER LOW VOLTAGE MANUFACTURING TRICKS
Low leakage device technologies. SOI (Silicon-On-Insulator) is a start, and
has been around a while in specialized processes. More recently, there's
been a lot of attention on fully-depleted devices -- which have far less
leakage because they cut off more avenues for electrons to leak.
There are two approaches to fully-depleted devices, both pioneered at the
same lab in UC Berkeley: Fully Depleted SOI (FD-SOI), and FinFETs. Which
is better depends who you ask. They can be combined too, for even better
leakage properties.
Dual-threshold or multi-threshold devices may help. The idea is to make
performance-critical devices run fast (hot), and all of the less-critical
devices run slow to reduce energy consumption. However, with ultra-low
voltage setups there may only be one threshold voltage available; and even
with more than one available, the benefit really depends on the circuit.
Post-silicon Trimming / Calibration. This is a widely used technique,
applied in amplifiers, voltage regulators, VCOs, PLLs, ADCs, and more.
The idea is, after manufacturing, to tune a circuit's voltage bias by, for
example, shorting one or more resistors in series. There are many variants.
Trimming can have major payoff, but has the risk of ballooning testing
effort or area. To mitigate that risk, it helps to measure the benefit of
trimming while still in design -- that is, use simulation to test the
effects of trimming on each Monte Carlo sample. There are techniques to
reduce testing effort, such as only trimming to meet specs on one temp.
(The tester would know from prior variation-aware simulation analysis that
by meeting that temperature, the circuit in question will work across whole
temperature range).
---- ---- ---- ---- ---- ---- ----
3. MEASURE ENERGY/PERFORMANCE/YIELD
Regardless of the devices/topology/architecture you're using, you must know
where you stand with respect to energy vs. performance. Furthermore, since
your voltage headroom is basically zero -- power and performance are now
more sensitive to process variation -- therefore tradeoffs with yield will
have to be considered.
When measuring energy and performance, one may model global variation simply
by ignoring it, using model sets like FF/SS, or by using a statistical
distribution. One may model local (mismatch) variation by ignoring it, or
using a distribution. Statistical global & local is the most accurate for
analog, memory, and custom digital circuits on modern processes.
Once one has these measurements, you can further optimize those measures by
changing device sizes. This isn't easy -- one cannot simply increase area
because that will drain power. You'll need insight into which transistors
to improve; and a fast way to iterate against design improvements. This is
where variation tools like Solido step in to do sensitivity analysis and
corner extraction while measuring energy/performance/yield. Then, while you
are sizing, you know which devices to tweak, and you only need to simulate
on a handful of extracted corners.
---- ---- ---- ---- ---- ---- ----
REAL LIFE EXAMPLE
In a recent example, a design team was working on a 28 nm clock distribution
network. Power was a primary constraint. Additionally, there were matching
constraints on the timing of the different (supposedly identical) cells in
the clock drives. The team found variation increased power use by 4x.
One perk of 28 nm is it's great for intrinsic high speed and low power use
with minimum size devices. However, these designers could not use the
minimum sized devices -- in mixed-signal circuits like data converters there
was too much variation on their delay. To meet the matching constraints,
the engineers had to increase the device sizes, which increased capacitive
load on the clock, and therefore wasted power. Ideally, the design team
would have removed the matching constraints altogether and added higher-
level variation analysis, for a potential 75% power savings.
Conclusion
Silicon is spreading to permeate the things around us. Yet our smartphones
still die. To address energy challenges of current and future devices,
ultra-low voltage analog is key.
- Trent McConaghy
Solido Design Vancouver, Canada
---- ---- ---- ---- ---- ---- ----
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