( ESNUG 532 Item 1 ) -------------------------------------------- [09/06/13]
Subject: MENT says Hogan missed emulation's all about power and cooling
> Category 1:
>
> - Cadence Palladium. Hats off to Cadence for being pioneers in
> emulation and sustaining innovation to maintain a very competitive
> product year-over-year.
>
> - Mentor Veloce. Their revenue numbers show emulation is a growing
> segment for them. (See ESNUG 510 #7.) Clearly Wally and Greg
> have been investing heavily in emulation.
>
> Category 2:
>
> - Synopsys EVE Zebu. This has been the choice for companies and
> design groups doing mid-size SoCs or blocks for emulation. It
> is no secret that Intel was an EVE customer. (See ESNUG 508 #6.)
> My expectation is that with the Synopsys acquisition, EVE will now
> move upstream to challenge Cadence and Mentor at the high end.
>
> - from http://www.deepchip.com/items/0522-04.html
From: [ Jim Kenney of Mentor ]
Hi, John,
Jim divided the emulator offerings between Boolean processors and FPGAs. I
think a more meaningful way to slice emulation would be full-custom chip
vs. off-the-shelf FPGA. This segmentation aligns best with user tangible
benefits. Veloce and Palladium both use custom chips designed specifically
for emulation and they share common characteristics that are distinct from
off-the-shelf FPGA systems like Synopsys/EVE Zebu.
|
|
Veloce 2
and
Palladium
|
Synopsys EVE Zebu
|
|
Speed
|
1 Mhz regardless of size
|
Above 1 MHz for a few FPGAs
Below 1 Mhz for multi-board
|
|
Capacity
|
Veloce delivered 2 B gates
Palladium delivered 512 M gates
|
EVE claims 1 B gates
|
Design
Compile
Success
|
~100%
|
Zebu often fails
|
Automatic
Partitioning
|
Fully automatic (no intervention)
|
Zebu often needs interventions
|
Debug
Visibility
|
Can see all nets, all of the time
|
Limited nets, requires recompile
|
Table 1: Summary of Veloce/Palladium vs. Synopsys EVE Zebu
---- ---- ---- ---- ---- ---- ----
SPEED VS. PARTITIONING FOR EVE ZEBU
Veloce and Palladium maintain ~1 MHz across a wide range of design sizes.
The design clock speed is typically limited by the longest combinatorial
path in the design. The custom chips are built with ample high-speed I/O
so 100 M gate designs are partitioned with minimal impact on emulation
speed.
EVE Zebu can approach 10 MHz on designs that fit in a few FPGAs, but slows
dramatically on designs partitioned across 10 or more FPGAs. Engineers
who have built their own FPGA prototypes experience this same slowdown as
the design is partitioned across many FPGAs.
---- ---- ---- ---- ---- ---- ----
PALLADIUM 2 BILLION GATE CAPACITY IMPRACTICAL
Mentor has delivered 2 B gate with Veloce Double Maximus. Cadence claims
about Palladium capacity are accurate on a per-chassis basis, but their
stated max of 2 B gates is impractical. At 64 M gates per Palladium GXL
chassis you'd need to cable together 32 GXLs to reach 2B gates. The photo
below shows a 4 GXL configuration of 256 M gates. Now picture a machine
8 times this size to reach 2 B gates. Hard to imagine how this could work,
or what the MTBF would be.
When EVE was EVE their capacity was overstated by nearly 2X. I've heard
Synopsys is reassessing EVE claims, but have seen no revisions published.
---- ---- ---- ---- ---- ---- ----
EVE ZEBU OFTEN CHOKES ON COMPILES
Veloce and Palladium seldom choke on a design compile nor do they produce
incorrect functional results because the chips and compiler were developed
in unison to do this specific result. In the rare case that a compile does
fail, it's considered a SW bug and fixed.
Because Veloce/Palladium design partitioning is fully automated, neither
system accepts user input on partitioning.
At multiple customer evals, I've seen EVE Zebu fail to complete the compile
phase. I've never experienced Veloce nor Palladium fail the compile phase
of an evaluation. (Yes, both systems have encountered compiler bugs that
required patches, but fully automated compile has always succeeded in the
time allotted by the customer.)
---- ---- ---- ---- ---- ---- ----
IT'S ALL ABOUT POWER, COOLING, AND FOOTPRINT
Where Veloce and Palladium diverge is the architecture of their full-custom
emulation ICs. Veloce models logic with LUTs (likely why Hogan put us in
the FPGA category) and Palladium uses Boolean processors. LUTs are 3X to
4X more compact and power efficient than Boolean processors as evidenced in
the photos below. No wonder Xilinx and Altera don't use Boolean processors!
At 256 M gates here's the major differences:
|
|
Veloce 2
|
Palladium
|
# of boxes
for 256 M gates
|
1 Quattro box
|
4 GXLs chassis
in 1 box
|
Power used
for 256 M gates
|
11 kW - air cooled
|
40 kW - liquid cooled
|
What 256 M gates
looks like
|
|
|
At 256 M gates, Mentor Veloce 2 uses 1/4 the power, 1/3 the footprint, and
1/4 the cooling Cadence Palladium does. That's 11 KW vs. 40 kW.
---- ---- ---- ---- ---- ---- ----
At 2 B gates the major differences get much more noticeable:
|
|
Veloce 2
|
Palladium
|
# of boxes
for 2 B gates
|
2 Double Maximus
chassis in 2 boxes
|
32 GXLs chassis
in 8 boxes
|
Power used
for 2 B gates
|
90 kW - air cooled
|
320 kW - liquid cooled
|
What 2 B gates
looks like
|
|
|
At 2 B gates, Mentor Veloce 2 uses 1/3.5 the power, 1/3 the footprint, and
1/3.5 the cooling Cadence Palladium does. That's 90 KW vs. 320 kW,
---- ---- ---- ---- ---- ---- ----
WE BOTH BAILED ON FPGA EMULATORS
While both Mentor (IKOS) and Cadence (Quickturn) had designed and sold FPGA-
based emulators in the past; we've both abandoned this architecture in favor
of full-custom ICs designed specifically for hardware emulation.
The benefits of a full-custom emulation IC include reliable compile, auto-
partitioning and unrestricted debug visibility.
Customers have shown their preference for full custom emulation by giving
a combined Veloce and Palladium 77% market share -- with only 23% going to
Eve Zebu's FPGA architecture. (Gary Smith EDA: 2011)
Mentor Veloce hit the emulation sweet spot by merging the certain compiles
and debug simplicity of full custom with the efficiency of a LUT-based
architecture. This is the key factor in our phenomenal growth (2013 is
already our 5th consecutive record growth year) and success in capturing
logos once dominated by Cadence and EVE.
- Jim Kenney
Mentor Graphics Corp. Wilsonville, OR
---- ---- ---- ---- ---- ---- ----
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