( ESNUG 532 Item 3 ) -------------------------------------------- [09/06/13]
From: [ Frank Schirrmeister of Cadence ]
Subject: CDNS says Hogan missed close to 10 emulation customer use models
Hi, John,
In ESNUG 522 #2, Jim Hogan talks about simulation acceleration. He points
out the key challenge correctly in acceleration performance is determined by
1) the percentage of the simulation that is left running in software,
2) the number of I/O signals communicating between the PC/workstation
and the hardware engine,
3) communication channel latency and bandwidth and
4) the amount of visibility enabled for the hardware being accelerated.
However, later in the table Jim then only mentions GPU acceleration by way
of Rocketick. One main use model of Palladium emulation is "Verification
Acceleration", in which the hardware DUT executes in the HW accelerator and
a portion of the design, typically its test bench, is kept in SW simulation.
Good examples for this use model are PMC Sierra at CDNLive 2012 achieving
40x speedup [Ref 6], Broadcom at DVCON 2011 achieving 230x speedup [Ref 7]
and Samsung at CDNLive 2013 achieving 410x speedup [Ref 8] -- all compared
to pure RTL simulation. In comparison, Rocketick's GPU acceleration was
featured in ESNUG 523 #1 as getting up to 23x speedup.
To better distinguish acceleration using GPUs from acceleration using
Emulation connected to RTL SW simulation, I suggest separating simulation
acceleration and verification acceleration in Jim's table as follows, the
bold red elements are my updates.
| | Computational Element
| Granularity (# of comp elements)
| Speed per comp element
| Cycles per Sec (100 M gates)
| Vendors
|
| SW Simulation
| X86 cores
| under 16
| 3 GHz
| under 1
| Cadence Incisive/NC-Sim, Synopsys VCS, Mentor Questa
|
| Simulation acceleration | GPU processing elements
| 100's
| 1 GHz
| 10 to 1,000
NVDIA: 17x
| Rocketick
|
| Verification Acceleration | Mix of Host and Emulator
| millions
| under 1 GHz
| 40 to 10,000
| Cadence Palladium XP + RTL Sim
Mentor Veloce + RTL Sim
Synopsys Zebu Server + RTL Sim
|
Processor
-based emulation | custom processors
| It is actually 100s of 1000s to millions
| under 1 GHz
| 100 K to 2M, processor based scales better with design size than FPGA
| Cadence Palladium
|
FPGA
-based emulation | FPGA gates
| millions
| 1 MHz - 100 MHz
| 500 K - 2 M, does not scale well with design size, so at 100MG to reach the M range is very unlikely. Debug causes further slow down.
| Mentor Veloce, Synopsys EVE-Zebu
|
| FPGA prototyping | FPGA gates
| millions
| 1 MHz - 100 MHz
| 2M - 50 M, sometimes up to 100M
| Synopsys HAPS, Cadence RPP, DINI, Aldec, S2C, HOENS, Hitech Global, ProDesign
|
Table 2: Various Types of HW Assisted Verification
There are three main customer use models in In-Circuit Emulation (ICE) and
Verification Acceleration:
1) functional verification
2) regression runs and
3) software development/validation for drivers, operating
system (OS) bring-up and middleware.
Besides these, there are many other customer use models like: performance
validation, post-silicon debug, test pattern preparation, failure analysis
and reproduction, and virtual silicon support making the "chip-to be"
available to customers for early access.
You can check out these use models at a recent case study: "Using Cadence
Palladium for SoC Performance Validation and Analysis" that Freescale gave
at CDNLive 2013 and later in similar form at DAC [Ref 9].
Two use models very unique to Palladium XP:
- Gate-Level Acceleration -- something FPGA-based emulators cannot
support due to the explosion in complexity in re-mapping the
target technology to FPGA gates, and
- Dynamic Low Power analysis.
For the latter your readers can check out last year's presentation "NS115
System Emulation Based on Palladium XP" given by Nufront [Ref 4] that won
the pest paper award at CDNLive Shangai last year. They booted Android,
achieved 1000x performance improvement over RTL simulation and correlated
power consumption using realistic runtime environments and applications
before silicon was available.
For your reader's convience, in Item 5, I've assembled a list of use models
together with sources and results users achieved with Palladium.
- Frank Schirrmeister
Cadence Design Systems, Inc. San Jose, CA
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Related Articles
CDNS says Hogan missed granularity, user access, speed, capacity
CDNS says Hogan missed FPGA compile time, Rent's Rule, probing
CDNS says Hogan missed 5 metrics/gotchas for picking an emulator
CDNS says Hogan missed 47 Palladium user papers on Cadence.com
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