( ESNUG 528 Item 4 ) -------------------------------------------- [09/12/13]
Subject: News & Rumors on TSMC, ARM, Intel, Apache, Solido, Laker, Tempus
BACK FROM SUMMER: Here's the latest news & rumors I've heard about EDA and
fabs since my prior post. Feel free to comment/correct/scold anything!
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- Showing the pain of TSMC losing Altera to Intel 14 nm (ESNUG 528 #1),
Ashraf Eassa, a SeekingAlpha.com analyst, did a detailed analysis
of the public claims TSMC management makes about their future nodes
and said he does "not believe that the claims that they are making
regarding their future technologies can be taken seriously."
Eassa said the TSMC comments: "represent at best a knee-jerk reaction
to the massive process technology lead that Intel has and the
pressure that its customers are putting on the company to deliver."
After going through the 28 nm ramp-up claims in the 2010-11 TSMC
earnings calls, Eassa then examined the TSMC 20 nm and 16 nm ramp-up
claims in their January 2013 earnings call. His overall conclusion:
"TSMC is a great company that is a leader in the foundry space,
but they are trying too hard to appease investors/customers
with some of these claims regarding FinFETs. On the January
call (before Intel took Altera and likely Cisco from TSMC),
the claim was "minimal volumes of 16 nm in 2015".
Now, TSMC is trying to pull a FinFAST one on investors and
customers by claiming that 16 nm will be in production during
2014, totally bypassing the yet-to-ramp 20 nm node.
I'm not buying these claims, and neither should you."
- Ashraf Eassa, SeekingAlpha.com, (05/30/13)
The title of Eassa's analysis was a scathing: "Taiwan Semiconductor
Tries To Pull A FinFAST One". (OUCH!) Rumor is the bigwigs in
Hsinchu are still furious, even months later, about this story.
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- During DAC week in June, ABI Research upset ARM Holdings, Ltd. when
it released a cell phone benchmark that accidentally had hard numbers
showing how poorly their ARM cores did vs. Intel's new Z2580 -- when
they were both doing the same thing -- running a high-end smartphone.
CPU Average CPU Peak
Current Use Current Use
Intel Z2580 Saltwell x2 2.0 Ghz 0.85 A 1.05 A
ARM A15 x2 1.7 Ghz 0.98 A 1.23 A
ARM A15 x4 + A7 x4 1.6 Ghz 1.38 A 1.71 A
ARM A15 x8 1.9 GhZ 1.79 A 2.10 A
Tegra 3 ARM A9 x4 1.3 Ghz 0.90 A 1.19 A
Only the Nvidia Tegra 3 running 35% slower at 1.3 Ghz had matched the
new Intel Z2580's low power use.
"The new processor not only outperformed the competition in
performance, but did so with up to 1/2 the current drain."
- Jim Mielke, VP of Engineering at ABI Research
Why this benchmark is significant is because ABI Research is a well
known teardown service that's been around since 1990. (ARM OUCH #1!)
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- Rumor is Simon Segars, the recent new CEO of ARM, caught hell from
his Board of Directors for paying $26 million to license the Sonics
patent portfolio -- yet Simon failed to beat Qualcomm to the punch
on acquiring Arteris. "A swing and a miss!" (ARM OUCH #2!)
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- Rumor is Synopsys ARC recently knocked out ARM in a major Japanese
automative vision design socket -- meaning a high volume design.
"How in the world we won the deal, no one will ever know ...
We were blown away. Stunned really."
- a rumored comment by George Zafiropoulos, the
Synopsys VP who owned DW ARC
So now Synopsys is nervous. This news will certainly add fuel to the
Cadence/ARM vs. Synopsys/ARC fire. Aart has tried to downplay this
ARC thing, but Segars isn't stupid. (ARM OUCH #3!)
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- Last I heard on the BDA vs. Cadence lawsuit is they're in the very
early stages of "discovery" and they both still hate each other.
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- FUN QUOTE:
"What's been up with Atoptech? I haven't heard any news about
them since Synopsys sued them 4 months ago.
While you're at it, what's been up with Mentor Olympus-SoC?
I haven't heard any news about them in over a year!"
- an EDA user
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- Solido 3.0 released today. Capacity was 100 K, now 20 M devices; and
Monte Carlo variables was 1 K, now 20 K. Claims tighter into Cadence
Virtuoso ADE (45 min load times are now 3 min load times). Was HSMC
on memory bit cells -- now on mem sense amps, mem columns/sub-arrays,
large analog blocks (eg. SerDes, DACs), and std cell library designs.
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- Real Intent Ascent Lint 2013 released today. Does 500 M logic gates,
22 new lint rules, Perl compatible regex, new CDC readiness policy,
a new Emacs mode, more support for SystemVerilog, Verilog and VHDL,
better GUI and "low-noise reporting of design issues".
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- FUN QUOTE:
Cooley: "Joe, does Carl Icahn regret investing in Mentor?"
Sawicki: "Well, just Thursday I was talking to Carl about
our 2012.4 release..."
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- Cadence and TSMC put out a joint press release in July that explicitly
said TSMC was going to use Virtuoso to develop its own internal IP;
meaning they were abandoning SpringSoft Laker for internal TSMC use???
("Why not? Laker's now Synopsys! Screw that! We only used it cause
it was a Taiwanese EDA company.") Inquiring minds want to know...
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- Word on PrimeTime street is recently two more (ex-Extreme-DA, then
ex-Magma, and now ex-SNPS) PrimeTime FAE's have jumped ship to join
Cadence to support Tempus. In addition, this week Sanjay Lall, a
rockstar EDA salesman based in Austin just joined the Cadence Tempus
team, too. Looks like Lip-Bu's serious about Tempus succeeding.
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- FUN QUOTE:
"Apache today is falling into the end-of-life product cycle.
So when you say we're an Apache wannabe, John, we take offense.
We're the better next generation EDA tools taking our rightful
place at the sub-20 nm table."
- Jens Andersen of Invarian (ESNUG 529 #5)
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- On Monday, Cadence launched Palladium XP II. Claims 2.3 B gates,
512 users, 2X faster overall, 60X faster OS boot, "shorten time
to market by 4 months", 5x faster debug compared to Veloce 2, plus
Cadence accelerated VIP for PCIe, SRIOV, Ethernet, AHB, APB, HDMI,
DSI, CSI, I2C, SimCard, and Keypad. Broadcom, Nvidia users.
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- Tesla Motors has standardized on the Mentor Capital auto harness
toolset for 12-volt electrical systems design. (Gotta wonder if
Wally managed to get a Tesla Roadster Sport 2.5 out of the deal?)
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- The Jasper User Group Meeting is coming up on Oct. 22-23 at the
Cypress Hotel in Cupertino, CA. They'll be having user-lead
Birds-of-a-Feathers on: Proof Grids, Property synthesis, IP-XACT,
Clock & Reset Set-up and verification, Low power verification,
AMBA Proofkit, Protocol verification, Security path verification.
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And again, feel free to comment/correct/scold/question anything you see here
by just emailing me directly. And, yes, you'll be ANONYMOUS!
- John Cooley
DeepChip.com Holliston, MA
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