( ESNUG 527 Item 4 ) -------------------------------------------- [07/11/13]
From: [ Trent McConaghy of Solido Design ]
Subject: Trent on DAC'13 papers on post-silicon, TSV, 3D IC, and SSTA
Hi, John,
Here's 6 papers on post-silicon testing analog/custom designs, wafers, TSVs,
3D ICs, plus SSTA.
- Trent McConaghy, CTO
Solido Design Automation Vancouver, Canada
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Paper: Multidimensional Analog Test Metrics Estimation using Extreme
Value Theory and Statistical Blockade
Authors: Haralampos Stratigopoulos et al. (TIMA Lab, InfiniScale)
Haralampos Stratigopoulos works on high-sigma (low failure rate) analog
test. His works draw on design tool research, leveraging mathematical
techniques like density estimation. He and I co-presented a tutorial at
DATE last year, showing the similarities among tools for high-sigma test and
high-sigma design. The paper’s contribution was to handle more than one
output at once, which is not trivial for some high-sigma approaches. The
paper leveraged:
1) Extreme Value Theory, which is a particular approach to density
estimation for high-sigma tails
2) Statistical Blockade, a CMU technique that continually draws
Monte Carlo samples but only simulates the promising ones.
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Paper: Automatic Clustering of Wafer Spatial Signatures
Authors: Wangyang Zhang et al. (CMU, PDF Solutions, U. Illinois)
During his PhD at CMU under Prof Xin Li and Prof R. Rutenbar, Wangyang
Zhang explored techniques to help process engineers make sense of wafer-
level variation. Each die in the wafer has test structures, e.g. to
measure NMOS drain saturation current I_dsat. Wangyang's previous work took
as input the I_dsat value and corresponding x,y location, across multiple
wafers; and then applied sparse regression across multiple basis functions.
The relative strength of different basis functions pointed to relative
importance of different yield loss mechanisms. Wangyang et al actually got
best paper in the IEEE TCAD journal last year for this work; and they were
presented with the award at DAC 2013. (Congrats!)
This year their DAC paper points out that different wafers have different-
looking patterns across the x-y space, but there tend to be some common
patterns. The approach automatically identifies the common patterns, by
combining sparse regression with bottom-up clustering.
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Paper: High-Throughput TSV Testing and Characterization for 3D
Integration Using Thermal Mapping
Authors: Kapil Dev, Gary Woods, and Sharief Rada (Brown U.)
Through-Silicon Vias (TSVs) are a hot topic of research as an enabler for 3D
ICs, a direction to help keep Moore's Law going. But variation affects TSV
resistance, and leads to faulty TSVs. Testing TSVs is a particular
challenge. One might consider testing TSVs before or after the chips get
joined together (bonding). But each has issues: testing before isn't very
thorough, and testing after might mean that a bad die has been coupled with
a good one. These authors propose using a thermal imaging camera to test
the electrical connectivity of TSVs. A resistive electrolyte solution is
on the back side of the device so that current can pass through the TSVs
and solution, and be detected by the camera. The result: accurate
high-throughput TSV testing.
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Paper: Effective and Efficient In-Field TSV Repair for Stacked 3D ICs
Authors: Li Jiang et al. (Chinese University, Duke U, Cisco)
These authors also explore TSV reliability, and in particular TSV failure
due to aging. One solution to TSV failure is to have TSVs for built-in
self-repair. Previous approaches were less appropriate for failures at
time > 0; that is where this paper makes a contribution with the "first
in-field TSV repair framework" and show how it improves the
mean-time-to-failure.
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Paper: Power and Signal Integrity Challenges in 3D Systems
Authors: Miguel Miranda et al. (Qualcomm)
These researchers look at exploring the design space of 2.5/3 D systems,
and the particular challenges of power integrity and signal integrity.
In short: many tools are needed for 2.5/3 D, and are currently missing.
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Paper: Speeding up Computation of the max/min of a set of Gaussians
for Statistical Timing Analysis and Optimization
Authors: Vimitha Kuruvilla et al. (IBM, IIT)
SSTA is all about propagating distributions for delay through the logic
network. Now and then these distributions have to get merged via an
approximate "max" function. Much of the SSTA literature, including this
paper, is about a faster or more accurate "max". This paper shows how
special handling of "zero error" cases gives a 3X speedup in max/min
operations, leading to 2-17% speedup in a single SSTA run, and up to 55%
improvement in SSTA optimization.
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