( ESNUG 527 Item 3 ) -------------------------------------------- [07/11/13]
From: [ Trent McConaghy of Solido Design ]
Subject: Trent on DAC'13 papers on analog and mixed-signal verification
Hi, John,
I chaired this year's DAC technical session on analog verification, which
had 4 papers.
- Trent McConaghy, CTO
Solido Design Automation Vancouver, Canada
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Paper: ABCD-L - Approximating Continuous Linear Systems Using
Boolean Models
Authors: Aadithya Karthik and Jaijeet Roychowdhury (UC Berkeley)
The general idea is to model the continuous dynamics of linear time
invariant systems using *just* Boolean approximations. Think of it like a
floating-point approximation (which is 32- or 64-bit binary), but with fewer
bits, because you don't need accuracy to 2^(-64). The work showed that just
5-8 bits was needed to accurately reproduce a dynamics of an RLGC filter,
RLGC chain, and an LTI channel + differential equalizer.
The approach actually has linear scaling, via a thoughtful problem
decomposition approach. This paper is complementary to the authors'
previous work on nonlinear systems. Together, the two works point to an
extremely interesting possibility: analog circuits being converted to purely
Boolean form, which opens up a fast, direct path for analog to fit into the
big-digital tool ecosystem.
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Paper: Verification of Digitally-Intensive Analog Circuits via
Kernel Ridge Regression and Hybrid Reachability Analysis
Authors: Honghuang Lin (Texas A&M), Peng Li (Texas A&M), and
Chris Myers (Univ. Utah)
This paper also aims to address analog verification. As Jaeha Kim pointed
out in this paper’s Q&A session, the UC Berkeley paper converts analog to
digital, while this paper converts digital to analog, both in the name of
efficiency! That said, the papers address somewhat different problems.
This paper aims for formal verification of AMS circuits, that is, to be
able to state "with some provability" that the circuit will converge to a
particular region in state space. In this work, the specific challenge was
to bring together the digital and analog portions of the AMS circuit. As
hinted above, the approach is to convert the digital portions to analog,
then to apply analog-centric reachability analysis. The paper added
further speedups via the machine learning technique of ridge regression.
The paper showed excellent results on a digitally-intensive phase-locked
loop (PLL).
Note: Formal analog verification has been an ongoing theme for
Chris Myers over the last decade; at DAC'13 he was awarded
an IEEE Fellowship for his work (congrats Chris!).
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Paper: Bayesian Model Fusion - Large-Scale Performance Modeling of
Analog and Mixed-Signal Circuits by Reusing Early-Stage Data
Authors: Fa Wang et al. (CMU)
This paper by Fa Wang et al. under professor Xin Li at CMU, with
collaboration from Chenjie Gu of Intel, continues a thread for Xin's group
across several papers at DAC and elsewhere: building regression models
mapping process variables to outputs, for analog and memory circuits having
thousands of process variables.
More recently Xin and his group have been leveraging the Bayesian
perspective which has become popular in machine learning; this perspective
allows them to incorporate prior knowledge with newly gathered data in a
clean mathematical framework. This paper incorporates both research
threads: using coefficients from a pre-layout regression model as prior
knowledge, to inform building a new regression model on post-layout data.
The result: the same accuracy as before, but up to 9x faster, on a ring
oscillator and an SRAM read path.
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Paper: Efficient Moment Estimation with Extremely Small Sample Size
via Bayesian Inference for Analog/Mixed-Signal Validation
Authors: Chenjie Gu (Intel) and Xin Li (CMU)
Chenjie Gu and Xin Li also collaborated on this paper. Let's say you want
to estimate the distribution of a circuit output, but you only have 3 or 5
or 8 samples of data. What can you do, if anything? The general approach,
as in paper 24.2, was to leverage prior knowledge via a Bayesian framework.
In this case, the prior knowledge is simulation data, and new knowledge is
silicon test data. The researchers show a 2x reduction in the number of
samples needed to get the same accuracy in estimating the mean and standard
deviation of a high speed I/O link's bit error rate (BER). This is actually
quite significant, given that the number of samples is so low, and that
gathering each additional sample is expensive.
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