( ESNUG 527 Item 2 ) -------------------------------------------- [07/11/13]
From: [ Trent McConaghy of Solido Design ]
Subject: Trent on DAC'13 papers on SPICE, fast SPICE, analog simulation
Hi, John,
Here's the 8 papers on SPICE, fast SPICE, analog simulation.
- Trent McConaghy, CTO
Solido Design Automation Vancouver, Canada
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Paper: TinySPICE - a parallel SPICE simulator on GPU for massively
repeated small circuit simulations
Authors: Lengfei Han et al. (Michigan Tech University)
Since the mid 2000's, several companies and universities have been
experimenting with GPUs for circuit simulation. All would agree that the
general idea is fantastic. But it hasn't yet materialized into successful
commercial simulators. (I say "successful" because Nascentric tried...
then went broke.) At ICCAD 2012, Duaune Pryor of Mentor Graphics explained
why (ESNUG 518 Item 6): latency and bandwidth issues make the potential
speedups "evaporate" in industrial implementations.
The idea proposed in the paper is to sidestep those issues by putting the
*whole simulator* into each single GPU thread, *only* on circuits small
enough to fit into the thread (e.g. standard cells, bitcells), and only
running small variants of the circuits on each thread (e.g. Monte Carlo
samples). To implement this idea, the researchers developed GPU-friendly
data structures and algorithm flow. Speedups range from 264x (for bitcell
Monte Carlo, with 20 unknowns) to 22x (for 4-input MUX, with 35 unknowns).
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Paper: Time-Domain Segmentation based Massively Parallel
Simulation for ADCs
Authors: Zuochang Ye (Tsinghua U), Song Han (Stanford), and
Yang Li (U Texas, Austin)
This paper looked at massively parallel simulation as well, but this time
analyzing a circuit once rather than multiple Monte Carlo samples. The
problem is the time-consuming nature of simulating the signal-to-noise and
distortion-ratio (SNDR) of analog-to-digital converters (ADCs) in transient.
The opportunity is that Flash and Successive Approximation (SAR) ADCs have
short memory. So the idea in the paper is to slice up the simulation job by
time segments, and to simulate all segments in parallel. Each simulation
has some overlap with other simulations, to account for startup / the
(short) memory.
- On a Flash ADC, the approach gave a 7.1x speedup on 8 cores, and a
64x speedup on 100 cores, with full SPICE accuracy.
- On a SAR ADC, the approach gave 7.2x speedup on 8 cores and 78x
speedup on 100 cores, with full SPICE accuracy.
- A Sigma-Delta ADC has longer memory and is less appropriate; but
the researchers did some algorithm tweaks and showed a 6.4x
speedup on 8 cores, 73.7x speedup on 100 cores, with <1% error
compared to SPICE.
The approach can be run on any off-the-shelf transient simulator, wrapped by
a simple script.
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Paper: A New Time-Stepping Method for Circuit Simulation
Authors: G. Peter Fang (Texas Instruments)
This research re-examined the very heart of simulation solvers -- time
steps. The iterative loop of traditional solvers is: first predict a time
step, then solve the circuit at that time step, and finally backtrack if
needed. However, if strong nonlinearity or an independent source causes
dynamics to change dramatically between time points, then the time step
prediction will be far off, causing excessive backtracking or needlessly
small step sizes.
This paper aimed to solve the problem by solving the time step and circuit
*simultaneously*. It also backtracks if needed, but less frequently.
- The best speedup was 48.0%, on an LDO, having 48.5% fewer time
points.
- The average speedup was 20.3%, with 40.3% fewer time points.
The paper also demonstrated how the method can simulate more accurately, or
equivalently, be less sensitive to user time step settings, because it does
not accumulate truncation error the way that traditional methods do.
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Paper: An Event-Driven Simulation Methodology for Integrated
Switching Power Supplies in SystemVerilog
Authors: Ji Eun Jang, Myeongjae Park, and Jaeha Kim (Seoul National Univ.)
How do you simulate a mixed-signal system efficiently? This remains an open
problem, but several research groups are making strong headway, including
this team at Seoul National University, Korea. Their general approach is to
thoughtfully subdivide mixed signal system, then automatically construct
good event-driven, continuous-valued models for the analog subcircuits.
Such models can be simulated efficiently in SystemVerilog, which means no
expensive SPICE solving. In this paper, they apply a single style of basis
function (a complex exponential) which changes its coefficient values at
each input or switching event. Using such models, the authors achieved
20-100x speedup simulating a power factor corrector circuit and a
switched-capacitor DC-DC converter, while retaining full SPICE accuracy.
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