( ESNUG 526 Item 1 ) -------------------------------------------- [06/28/13]

Subject: Joe Costello on Oasys, Montana, EDA, Design Compiler, estimation




     




                DAC'13 Troublemaker's Panel in Austin, TX

     Joe Costello of Oasys discusses what he's doing back in EDA after
     being away for 15 years, investing in EDA, Oasys synthesis faster
     than Synopsys Design Compiler, Montana super fast simulation
     that's not emulation, Oasys' new estimation tool approach, but
     Oasys still also doing RTL synthesis, tape-outs, RTL radar, less
     loops needed in iteration, early detail in hours, going for #4 as
     in the EDA Big 4, standing on its own, "it takes someone who's
     good at merging EDA companies together" -- BIG HINT!

   !!!     "It's not a BUG,
  /o o\  /  it's a FEATURE!"
 (  >  )
  \ - / 
  _] [_     (jcooley 1991)